MAX817_CSA 查看數據表（PDF） - Maxim Integrated

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MAX817_CSA

+5V Microprocessor Supervisory Circuits

Maxim Integrated 

+5V Microprocessor Supervisory Circuits

______________________________________________________________Pin Description

MAX817

PIN

MAX818

MAX819

1

1

1

2

2

2

3

3

3

4

—

4

—

4

—

5

—

5

—

5

—

6

6

—

—

—

6

7

7

7

8

8

8

NAME

OUT

VCC

GND

PFI

CE IN

PFO

CE OUT

WDI

MR

RESET

BATT

FUNCTION

Supply Output for CMOS RAM. When VCC rises above the reset threshold

or above VBATT, OUT is connected to VCC through an internal P-channel

MOSFET switch. When VCC falls below VBATT, BATT connects to OUT.

Input Supply Voltage, +5V input.

Ground. 0V reference for all signals.

Power-Fail Comparator Input. When VPFI is below VPFT or when VCC is below

VBATT, PFO goes low; otherwise, PFO remains high (see Power-Fail Comparator

section). Connect to ground if unused.

Chip-Enable Input. The input to the chip-enable gating circuit. Connect to

ground if unused.

Power-Fail Comparator Output. When PFI is less than VPFT or when VCC is

below VBATT, PFO goes low; otherwise PFO remains high. PFO is also used to

enable the battery freshness seal (see Battery Freshness Seal and Power-Fail

Comparator sections).

Chip-Enable Output. CE OUT goes low only if CE IN is low while reset is not

asserted. If CE IN is low when reset is asserted, CE OUT will remain low for

15µs or until CE IN goes high, whichever occurs first. CE OUT is pulled up to

OUT in battery-backup mode. CE OUT is also used to enable the battery

freshness seal (see Battery Freshness Seal section).

Watchdog Input. If WDI remains either high or low for longer than the watch-

dog timeout period, the internal watchdog timer runs out and a reset is trig-

gered. If WDI is left unconnected or is connected to a high-impedance

three-state buffer, the watchdog feature is disabled. The internal watchdog

timer clears whenever reset is asserted, WDI is three-stated, or WDI sees a ris-

ing or falling edge. The WDI input is designed to be driven by a three-stated-

output device with a maximum high-impedance leakage current of 10µA and a

maximum output capacitance of 200pF. The output device must also be capa-

ble of sinking and sourcing 200µA when active.

Manual Reset Input. A logic low on MR asserts reset. Reset remains asserted

for as long as MR is held low and for 200ms after MR returns high. The active-

low input has an internal 63kΩ pull-up resistor. It can be driven from a TTL- or

CMOS-logic line or shorted to ground with a switch. Leave open, or connect to

VCC if unused.

Active-Low Reset Output. Pulses low for 200ms when triggered and remains

low whenever VCC is below the reset threshold or when MR is a logic low. It

remains low for 200ms after VCC rises above the reset threshold, the watchdog

triggers a reset, or MR goes low to high.

Backup-Battery Input. When VCC falls below VBATT, OUT switches from VCC to

BATT. When VCC rises above VBATT, OUT reconnects to VCC.

_______________________________________________________________________________________ 7

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