MAX817LEPA 查看數據表（PDF） - Maxim Integrated

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MAX817LEPA

+5V Microprocessor Supervisory Circuits

Maxim Integrated 

+5V Microprocessor Supervisory Circuits

_______________Detailed Description

General Timing Characteristics

Designed for 5V systems, the MAX817/MAX818/

MAX819 provide a number of microprocessor (µP)

supervisory functions (see the Selector Guide on the

first page). Figure 2 shows the typical timing relation-

ships of the various outputs during power-up and

power-down with typical VCC rise and fall times.

RESET Output

A µP’s reset input starts the µP in a known state. The

MAX817/MAX818/MAX819 µP supervisory circuits

assert a reset to prevent code-execution errors during

power-up, power-down, and brownout conditions.

RESET is guaranteed to be a logic low for 0V < VCC <

VRST if VBATT is greater than 1V. Without a backup bat-

tery (VBATT = GND) RESET is guaranteed valid for

VCC ≥ 1V. Once VCC exceeds the reset threshold an

internal timer keeps RESET low for the reset timeout

period, tRP. After this interval RESET returns high

(Figure 2).

If a brownout condition occurs (VCC drops below the

reset threshold), RESET goes low. Each time RESET is

asserted it stays low for at least the reset timeout peri-

od. Any time VCC goes below the reset threshold the

internal timer clears. The reset timer starts when VCC

returns above the reset threshold. RESET both sources

and sinks current.

Manual Reset Input (MAX819)

Many µP-based products require manual reset capabil-

ity, allowing the operator, a test technician, or external

logic circuitry to initiate a reset. On the MAX819, a logic

low on MR asserts reset. Reset remains asserted while

MR is low, and for tRP (200ms) after it returns high.

During the reset timeout period (tRP), MR’s state is

ignored if the battery freshness seal is enabled. MR has

an internal 63kΩ pull-up resistor, so it can be left open

if not used. This input can be driven with TTL/CMOS-

logic levels or with open-drain/collector outputs.

Connect a normally open momentary switch from MR to

GND to create a manual reset function; external

debounce circuitry is not required. If MR is driven from

long cables or the device is used in a noisy environ-

ment, connect a 0.1µF capacitor from MR to GND to

provide additional noise immunity.

Note that MR must be high or open to enable the bat-

tery freshness seal. Once the battery freshness seal is

enabled its operation is unaffected by MR.

Battery Freshness Seal

The MAX817/MAX818/MAX819 battery freshness seal

disconnects the backup battery from internal circuitry

and OUT until it is needed. This allows an OEM to

ensure that the backup battery connected to BATT will

be fresh when the final product is put to use. To enable

the freshness seal on the MAX817 and MAX819:

1) Connect a battery to BATT.

2) Ground PFO.

3) Bring VCC above the reset threshold and hold it

there until reset is deasserted following the reset

timeout period.

4) Bring VCC down again (Figure 3).

Use the same procedure for the MAX818, but ground

CE OUT instead of PFO. Once the battery freshness

seal is enabled (disconnecting the backup battery from

internal circuitry and anything connected to OUT), it

remains enabled until VCC is brought above VRST.

VBATT

VRST

VCC

VOUT

VBATT

tRP

VRESET

VRST

PFO FOLLOWS PFI

VPFO*

VCE OUT**

VBATT

CE OUT FOLLOWS CE IN

*MAX817/MAX819 ONLY.

** MAX818 ONLY.

Figure 2. Power-Up and Power-Down Timing

VBATT

RESET TO

CE OUT

DELAY**

VRST

VRST

VCC

RESET

CE OUT (MAX818)

(EXTERNALLY HELD AT 0V)

PFO (MAX817/MAX819)

(EXTERNALLY HELD AT 0V)

tRP

CE OUT STATE LATCHED

AT 1/2 tRP AND 3/4 tRP,

FRESHNESS SEAL ENABLED

PFO STATE LATCHED

AT 1/2 tRP AND 3/4 tRP,

FRESHNESS SEAL ENABLED

Figure 3. Battery Freshness Seal Timing

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