MAX9320EUA(2001) 查看數據表（PDF） - Maxim Integrated
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MAX9320EUA Datasheet PDF : 9 Pages
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1:2 Differential LVPECL/LVECL/HSTL
Clock and Data Drivers
PIN
TSSOP/SO
1
2
3
4
5
6
7
SOT23
8
7
6
5
2
4
3
8
1
NAME
Q0
Q0
Q1
Q1
VEE
D
D
VCC
Pin Description (MAX9320)
FUNCTION
Noninverting Q0 Output. Typically terminate with 50Ω resistor to VCC - 2V.
Inverting Q0 Output. Typically terminate with 50Ω resistor to VCC - 2V.
Noninverting Q1 Output. Typically terminate with 50Ω resistor to VCC - 2V.
Inverting Q1 Output. Typically terminate with 50Ω resistor to VCC - 2V.
Negative Supply Voltage
Inverting Differential Input. 60kΩ pullup to VCC and 100kΩ pulldown to VEE.
Noninverting Differential Input. 100kΩ pulldown to VEE.
Positive Supply Voltage. Bypass from VCC to VEE with 0.1µF and 0.01µF ceramic
capacitors. Place the capacitors as close to the device as possible with the smaller
value capacitor closest to the device.
PIN
SOT23
1
2
3
4
5
6
7
8
NAME
VCC
VEE
D
D
Q1
Q1
Q0
Q0
Pin Description (MAX9320A)
FUNCTION
Positive Supply Voltage. Bypass from VCC to VEE with 0.1µF and 0.01µF ceramic
capacitors. Place the capacitors as close to the device as possible with the smaller value
capacitor closest to the device.
Negative Supply Voltage
Inverting Differential Input. 60kΩ pullup to VCC and 100kΩ pulldown to VEE.
Noninverting Differential Input. 100kΩ pulldown to VEE.
Inverting Q1 Output. Typically terminate with 50Ω resistor to VCC - 2V.
Noninverting Q1 Output. Typically terminate with 50Ω resistor to VCC - 2V.
Inverting Q0 Output. Typically terminate with 50Ω resistor to VCC - 2V.
Noninverting Q0 Output. Typically terminate with 50Ω resistor to VCC - 2V.
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