MAX9320B 查看數據表（PDF） - Maxim Integrated
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MAX9320B Datasheet PDF : 7 Pages
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1:2 Differential PECL/ECL/LVPECL/LVECL
Clock and Data Driver
Detailed Description
The MAX9320B low-skew, 1-to-2 differential driver is
designed for clock and data distribution. For interfacing
to differential PECL and LVPECL signals, this device
operates over a +3.0V to +5.5V supply range, allowing
high-performance clock and data distribution in sys-
tems with a nominal 3.3V or 5V supply. For differential
ECL and LVECL operation, this device operates from a
-3.0V to -5.5V supply.
Inputs
The maximum magnitude of the differential input from D
to D is 3.0V. This limit also applies to the difference
between any reference voltage input and a single-
ended input.
The differential inputs have bias resistors that drive the
outputs to a differential low when the inputs are open.
The inverting input, D, is biased with a 50kΩ pullup to
VCC and a 100kΩ pulldown to VEE. The noninverting
input, D, is biased with an 80kΩ pullup to VCC and a
60kΩ pulldown to VEE.
Specifications for the high and low voltages of the dif-
ferential input (VIHD and VILD) and the differential input
voltage (VIHD - VILD) apply simultaneously (VILD cannot
be higher than VIHD).
Outputs
Output levels are referenced to VCC and are consid-
ered PECL/LVPECL or ECL/LVECL, depending on the
level of the VCC supply. With VCC connected to a posi-
tive supply and VEE connected to GND, the outputs are
PECL/LVPECL. The outputs are ECL/LVECL when VCC
is connected to GND and VEE is connected to a nega-
tive supply.
A differential input of at least ±100mV switches the out-
puts to the VOH and VOL levels specified in the DC
Electrical Characteristics table.
Applications Information
Supply Bypassing
Bypass VCC to VEE with high-frequency surface-mount
ceramic 0.1µF and 0.01µF capacitors in parallel as
close to the device as possible, with the 0.01µF value
capacitor closest to the device. Use multiple parallel
ground vias for low inductance.
Traces
Input and output trace characteristics affect the perfor-
mance of the MAX9320B. Connect each signal of a differ-
ential input or output to a 50Ω characteristic impedance
trace. Minimize the number of vias to prevent impedance
discontinuities. Reduce reflections by maintaining the
50Ω characteristic impedance through connectors and
across cables. Reduce skew within a differential pair by
matching the electrical length of the traces.
Output Termination
Terminate outputs through 50Ω to VCC - 2V or use an
equivalent Thevenin termination. Terminate both out-
puts and use the same termination on each for the low-
est output-to-output skew. When a single-ended signal
is taken from a differential output, terminate both out-
puts. For example, if Q0 is used as a single-ended out-
put, terminate both Q0 and Q0.
Chip Information
TRANSISTOR COUNT: 182
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