MB15F02L 查看數據表（PDF） - Fujitsu

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MB15F02L

Dual Serial Input PLL Frequency Synthesizer

Fujitsu 

4. Serial Data Input Timing

1st. data

Data

MSB

MB15F02L

2nd. data

Control bit Invalid data

LSB

Clock

LE

Parameter

t1

t2

t3

t4

t1

t2

t5

t7

t4

t3

t6

On rising edge of the clock, one bit of the data is transferred into the shift register.

Min.

20

20

30

20

Typ. Max.

–

–

–

–

–

–

–

–

Unit

ns

ns

ns

ns

Parameter

t5

t6

t7

Min.

30

100

100

Typ. Max.

–

–

–

–

–

–

Unit

ns

ns

ns

11

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