MB15F05L 查看數據表（PDF） - Fujitsu

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MB15F05L

Dual Serial Input PLL Frequency Synthesizer

Fujitsu 

MB15F05L

Programmable Counter

LSB

Data Flow

MSB

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

CC L S F A A A A A A A N N N N N NN NN NN

N N D W C 1 2 3 4 5 6 7 1 2 3 4 5 6 7 8 9 10 11

1 2 S RF RF

CN1, 2

: Control bit

N1 to N11 : Divide ratio setting bits for the programmable counter (5 to 2,047)

A1 to A7 : Divide ratio setting bits for the swallow counter (0 to 127)

SWRF

: Divide ratio setting bit for the RF prescaler0

FCRF

: Phase control bit for the RF phase detector

LDS

: LD/fout signal select bit

Note: Data input with MSB first.

[Table. 1]

[Table. 4]

[Table. 5]

[Table. 6}

[Table. 7]

[Table. 8]

Table2. Binary 14-bit Programmable Reference Counter Data Setting

Divide

ratio

(R)

5

6

·

16383

RRRRRRRRRRRRRR

14 13 12 11 10 9 8 7 6 5 4 3 2 1

00000000000101

00000000000110

·

·

·

·

·

·

·

·

·

·

·

·

·

·

11111111111111

Note: • Divide ratio less than 5 is prohibited.

Table.3 Test Purpose Bit Setting

T

T

1

2

L

L

H

L

L

H

H

H

LD/fout pin state

Outputs frIF.

Outputs frRF.

Outputs fpIF.

Outputs fpRF.

9

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