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MB95FV100D-101 查看數據表(PDF) - Fujitsu

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MB95FV100D-101
Fujitsu
Fujitsu Fujitsu
MB95FV100D-101 Datasheet PDF : 68 Pages
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MB95160 Series
(Continued)
UART/SIO × 1 channel
• Clock asynchronous (UART) or clock synchronous (SIO) serial data transfer capable
• Full duplex double buffer
I2C × 1 channel
Built-in wake-up function
External interrupt × 8 channels
• Interrupt by edge detection (rising, falling, or both edges can be selected)
• Can be used to recover from low-power consumption (standby) modes.
8/10-bit A/D converter × 8 channels
8-bit or 10-bit resolution can be selected.
LCD controller (LCDC)
• 32 SEG × 4 COM (Max 128 pixels) (Built-in internal division resistance product)
• With blinking function
Low-power consumption (standby) mode
• Stop mode
• Sleep mode
• Watch mode
• Timebase timer mode
I/O port
• The number of maximum ports : Max 53
• Port configuration
- General-purpose I/O ports (N-ch open drain) : 2 ports
- General-purpose I/O ports (CMOS)
: 51 ports
Programmable input voltage levels of port
CMOS input level/hysteresis input level
Flash memory security function (Flash memory device only)
Protects the content of Flash memory
2
DS07-12618-2E

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