MC-4516CB64PS-A10B 查看數據表（PDF） - NEC => Renesas Technology
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MC-4516CB64PS-A10B
NEC => Renesas Technology
MC-4516CB64PS-A10B Datasheet PDF : 16 Pages
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Byte No.
Function Described
31 Module bank density
32 Command and address setup time
33 Command and address hold time
34 Data signal input setup time
35 Data signal input hold time
36-61
62 SPD revision
63 Checksum for bytes 0 - 62
64-71 Manufacture’s JEDEC ID code
72 Manufacturing location
73-90 Manufacture’s P/N
91-92 Revision code
93-94 Manufacturing date
95-98 Assembly serial number
99-125 Mfg specific
126 Intel specification frequency
127 Intel specification /CAS latency support
MC-4516CB64ES, 4516CB64PS
(2/2)
Hex Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Notes
20H 0
0
1
0
0
0
0
0 128 M bytes
25H 0
0
1
0
0
1
0
1 2.5 ns
10H 0
0
0
1
0
0
0
0 1 ns
25H 0
0
1
0
0
1
0
1 2.5 ns
10H 0
0
0
1
0
0
0
0 1 ns
00H 0
0
0
0
0
0
0
0
12H 0
0
0
1
0
0
1
0 1.2 A
BEH 1
0
1
1
1
1
1
0
66H 0
1
1
0
0
1
1
0 66 MHz
C7H 1
1
0
0
0
1
1
1
Timing Chart
Refer to the SYNCHRONOUS DRAM MODULE TIMING CHART Information (M13348E).
Data Sheet M13611EJ5V0DS00
11
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