MC100LVEL37DWR2(2000) 查看數據表（PDF） - ON Semiconductor
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MC100LVEL37DWR2 Datasheet PDF : 8 Pages
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MC100LVEL37
AC CHARACTERISTICS VCC= 3.3 V; VEE= 0.0 V or VCC= 0.0 V; VEE= –3.3 V (Note 1.)
–40°C
25°C
Symbol
Characteristic
Min Typ Max Min Typ Max Min
fmax
Maximum Toggle Frequency
TBD
TBD
tPLH
Propagation Delay
tPHL
CLK to Q/Q (Diff) 640
CLK to Q/Q 620
MR to Q 640
940 680 700 920 720
920 680 700 940 720
920 680 700 920 720
tSKEW
Within-Device Skew (Note 2.)
Duty Cycle Skew (Diff) (Note 3.)
50
50
50
50
tJITTER Cycle–to–Cycle Jitter
TBD
TBD
VPP
Input Swing (Note 4.)
150
1000 150
1000 150
tr
Output Rise/Fall Times Q
tf
(20% – 80%)
280
550 280
550 280
1. VEE can vary ±0.3 V.
2. Within-device skew defined as identical transitions on similar paths through a device.
3. Duty cycle skew is the difference between a TPLH and TPHL propagation delay through a device.
4. VPP(min) is minimum input swing for which AC parameters guaranteed. The device has a DC gain of ≈40.
85°C
Typ
TBD
TBD
Max Unit
GHz
ps
980
970
980
50
ps
50
ps
1000 mV
550 ps
Driver
Device
Q
Qb
50 W
D
Receiver
Device
Db
50 W
V TT
V TT = V CC – 2.0 V
Figure 1. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 – Termination of ECL Logic Devices.)
Resource Reference of Application Notes
AN1404
– ECLinPS Circuit Performance at Non–Standard VIH Levels
AN1405
– ECL Clock Distribution Techniques
AN1406
– Designing with PECL (ECL at +5.0 V)
AN1503
– ECLinPS I/O SPICE Modeling Kit
AN1504
– Metastability and the ECLinPS Family
AN1560
– Low Voltage ECLinPS SPICE Modeling Kit
AN1568
– Interfacing Between LVDS and ECL
AN1596
– ECLinPS Lite Translator ELT Family SPICE I/O Model Kit
AN1650
– Using Wire–OR Ties in ECLinPS Designs
AN1672
– The ECL Translator Guide
AND8001 – Odd Number Counters Design
AND8002 – Marking and Date Codes
AND8020 – Termination of ECL Logic Devices
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