MC10138FN 查看數據表（PDF） - ON Semiconductor
零件编号
产品描述 (功能)
生产厂家
MC10138FN Datasheet PDF : 8 Pages
| |||
MC10138
ELECTRICAL CHARACTERISTICS (continued)
NOTE: Each MECL 10,000 series circuit has
been designed to meet the dc specifications
shown in the test table, after thermal
equilibrium has been established. The circuit
is in a test socket or mounted on a printed
circuit board and transverse air flow greater
than 500 linear fpm is maintained. Outputs are
terminated through a 50–ohm resistor to –2.0
volts. Test procedures are shown for only one
gate. The other gates are tested in the same
manner.
@ Test Temperature
–30°C
+25°C
+85°C
VIHmax
–0.890
–0.810
–0.700
TEST VOLTAGE VALUES (Volts)
VILmin
–1.890
VIHAmin
–1.205
VILAmax
–1.500
–1.850
–1.105
–1.475
–1.825
–1.035
–1.440
VEE
–5.2
–5.2
–5.2
Characteristic
Power Supply Drain Current
Input Current
Symbol
IE
IinH
Pin
Under
Test
8
12
5,6,10,11
7
9
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
VIHmax
9
VILmin
VIHAmin
VILAmax
VEE
8
12
8
5,6,10,11
8
7
8
9
8
(VCC)
Gnd
1, 16
1, 16
1, 16
1, 16
1, 16
Output Voltage
Logic 1
IinL
VOH
All
3,14 (3.)
2,4,13,15 (2.)
9
5,6,10,11
Note 1.
8
1, 16
8
1, 16
8
1, 16
Output Voltage
Logic 0 VOL
3,14 (2.)
5,6,10,11
2,4,13,15 (3.)
9
8
1, 16
8
1, 16
Threshold Voltage
Logic 1 VOHA
2,4,13,15 (2.)
3,14 (3.)
13,15 (2.)
5,6,10,11
9
7,12
8
1, 16
8
1, 16
8
1, 16
Threshold Voltage
Logic 0 VOLA
2,4,13,15 (3.)
3,14 (2.)
13,15 (3.)
5,6,10,11
8
9
8
7,12
8
1, 16
1, 16
1, 16
Switching Times (50Ω Load)
Pulse In Pulse Out –3.2 V
+2.0 V
Propagation Delay Clock Delays t12+15+
15
t12+14+
14
t7+13+
13
t7+4+
4
t7+2+
2
t7+3+
3
t12+15–
15
t12+14–
14
t7+13–
13
t7+4–
4
t7+2–
2
t7+3–
3
Set Delay
t11+15+
15
t11+14–
14
Reset Delay
t9+14+
14
t9+15–
15
Rise Time
(20 to 80%) t14+
14
t15+
15
Fall Time
(20 to 80%) t14–
14
t15–
15
Counting Frequency
fcount
2
15
12
15
12
14
7
13
7
4
7
2
7
3
12
15
12
14
7
13
7
4
7
2
7
3
11
15
11
14
9
14
9
15
11
14
11
15
9
14
9
15
7
2
12
15
8
1, 16
8
1, 16
8
1, 16
8
1, 16
8
1, 16
8
1, 16
8
1, 16
8
1, 16
8
1, 16
8
1, 16
8
1, 16
8
1, 16
8
1, 16
8
1, 16
8
1, 16
8
1, 16
8
1, 16
8
1, 16
8
1, 16
8
1, 16
8
1, 16
8
1, 16
1. Individually test each input; apply VILmin to pin under test.
2. Set all four flip–flops by applying pulse
VIHmax
VILmin
3. Reset all four flip–flops by applying pulse
VIHmax
VILmin
to pins 5, 6, 10, and 11 prior to applying test voltage indicated.
to pin 9 prior to applying test voltage indicated.
http://onsemi.com
4
Share Link: 