ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Characteristic
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Output Rise Time A or B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tTLH = (3.0 ns/pF) CL + 30 ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tTLH = (1.5 ns/pF) CL + 15 ns
tTLH = (1.1 ns/pF) CL + 10 ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Output Fall Time A or B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tTHL = (1.5 ns/pF) CL + 25 ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tTHL = (0.75 ns/pF) CL + 12.5 ns
tTHL = (0.55 ns/pF) CL + 9.5 ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Propagation Delay Time
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ A (B) Synchronous Parallel Data Input,
B (A) Parallel Data Output
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tPLH, tPHL = (1.7 ns/pF) CL + 440 ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tPHL, tPHL = (0.66 ns/pF) CL + 172 ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tPLH, tPHL = (0.5 ns/pF) CL + 120 ns
Propagation Delay Time
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ A (B) Asynchronous Parallel Data Input
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ B (A) Parallel Data Output
tPLH, tPHL = (1.7 ns/pF) CL + 420 ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tPLH, tPHL = (0.66 ns/pF) CL + 147 ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tPLH, tPHL = (0.5 ns/pF) CL + 105 ns
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Clock Pulse Width
Symbol
tTLH
tTHL
tPLH,
tPHL
tPLH,
tPHL
tWH
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Clock Pulse Frequency
fcl
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Clock Pulse Rise
tTLH, tTHL
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ A, B Input Setup Time
tsu
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ High Level SE, P/S, A/S Pulse Width
tWH
VDD
Vdc
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
Min
Typ #
Max
Unit
ns
—
180
360
—
90
180
—
65
130
ns
—
100
200
—
50
100
—
40
80
ns
—
525
1050
—
205
410
—
145
290
ns
—
505
1010
—
180
360
—
130
260
340
170
140
70
110
55
—
ns
—
—
—
2.5
1.2
MHz
—
6.0
3.0
—
8.0
4.0
—
—
15
µs
—
—
5
—
—
4
100
35
45
15
35
12
—
ns
—
—
600
200
270
90
200
80
—
ns
—
—
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
TRUTH TABLE
“A” Enable P/S
A/B
A/S
Mode
Operation†
0
0
0
X
Serial Synchronous Serial data input, A and B Parallel data outputs disabled.
0
0
1
X
Serial Synchronous Serial data input, B–Parallel data output.
0
1
0
0
Parallel B Synchronous Parallel data inputs, A–Parallel data outputs disabled.
0
1
0
1
Parallel B Asynchronous Parallel data inputs, A–Parallel data outputs disabled.
0
1
1
0
Parallel A–Parallel data inputs disabled, B–Parallel data outputs.
0
1
1
1
Parallel A–Parallel data inputs disabled, B–Parallel data outputs.
1
0
0
X
Serial Synchronous serial data input, A–Parallel data output.
1
0
1
X
Serial Synchronous serial data input, B–Parallel data output.
1
1
0
0
Parallel B–Synchronous Parallel data input, A–Parallel data output.
1
1
0
1
Parallel B–Asynchronous Parallel data input, A–Parallel data output.
1
1
1
0
Parallel A–Synchronous Parallel data input, B–Parallel data output.
1
1
1
1
Parallel A–Asynchronous Parallel data input, B–Parallel data output.
X = Don’t Care
†Outputs change at positive transition of clock in the serial mode and when the A/S input is low in the parallel mode. During transfer from parallel
to serial operation, A/S should remain low in order to prevent DS transfer into flip–flops.
MOTOROLA CMOS LOGIC DATA
MC14034B
137