MC14034 查看數據表（PDF） - Motorola => Freescale

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MC14034

8-Bit Universal Bus Register

Motorola => Freescale 

EXPANDED BLOCK DIAGRAM

SERIAL DATA INPUT

ENABLE A

A/B

PARALLEL/SERIAL P/S

ASYN/SYN A/S

CLOCK

CONTROL

LOGIC

DATA

A1 A2 A3 A4 A5

A6 A7 A8

8–BIT REGISTER

B1 B2 B3 B4 B5

DATA

B6 B7 B8

OPERATING CHARACTERISTICS

The MC14034B is composed of eight register cells con-

nected in cascade with additional control logic. Each register

cell is composed of one “D” master–slave flip–flop with sepa-

rate internal clocks, and two data transfer gates allowing the

data to be transferred bi–directionally from bus A to bus B

and from bus B to bus A, and to be memorized. Besides the

single phase clock and the serial data inputs, the control log-

ic provides four other features:

A Enable Input — When high, this input enables the bus A

data lines.

A/B Input (Data A or B) — This input controls the direc-

tion of data flow: when high, the data flows from bus A to bus

B; when low, the data flows from bus B to bus A.

P/S Input (Parallel/Serial) — This input controls the data

input mode (parallel or serial). When high, the data is trans-

ferred to the register in a parallel asynchronous mode or a

parallel synchronous mode (positive clock transition). When

low, the data is entered into the register in a serial synchro-

nous mode (positive clock transition).

A/S Input (Asynchronous/Synchronous to the Clock)

— When this input is high, the data is transferred indepen-

dently from the clock rate; when low, the clock is enabled and

the data is transferred synchronously.

LOGIC DIAGRAM

A1

A2 A3 A4 A5 A6 A7

A8

16

17 18 19 20 21 22

23

A ENABLE 9

A/B 11

SERIAL DATA 10

PARALLEL SERIAL 13

ASYN/SYN 14

CLOCK 15

VDD

*D FLIP FLOP

CM

CS

VDD

6 STAGES

(SAME AS

STAGE 1)

VDD

*D

FLIP–

FLOP

DQ

CM CS

8

7 6543 2

1

B1

B2 B3 B4 B5 B6 B7

B8

MC14034B

138

MOTOROLA CMOS LOGIC DATA

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