MC141585 查看數據表（PDF） - Motorola => Freescale
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MC141585 Datasheet PDF : 27 Pages
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- C means column byte.
- I means data byte.
- In format (c), one dummy data byte(col 31) has
to be inserted after the row attribute data byte
(col 30) at end of each row, before the first
character attribute data byte of the next row.
To differentiate the row address for attribute/control regis-
ters from display area when transferring data, the most sig-
nificant three bits are set to ‘101’ to represent the row
address of the attribute/control registers, while ‘00X’ for col-
umn address used in format (a) or (b) and ‘01X’ for column
address used in format (c). There is some limitation on using
mix-formats during a single transmission. It is permissible to
change the format from (a) to (b), or from (a) to (c), or from
(b) to (a), but not from (c) back to (a) or (b).
row addr col addr
info
Figure 7. Data Packet for Attribute/Control Data
0
0
27 28 29 30
0
0
COLUMN
27 28 29
DISPLAY REGISTERS
14
Figure 9. Memory Map of Display Registers
Internal display RAM are addressed with row and column
(coln) number in sequence. As the display area is 15 rows
by 30 columns, the related display registers are also 15 by
30. The space between row 0 and coln 0 to row 14 and coln
29 are called Display registers, with each contains a charac-
ter/symbol address corresponding to display location on
monitor screen. And each register is 8-bit wide to identify the
selected character/symbol out of 256 logical selected ROM
fonts.
CHARACTER ATTRIBUTE REGISTERS
0
0
COLUMN
27 28 29 30
14
0
11 12
18 19
31
15 WINDOW 1 ~ WINDOW 4 FRAME CRTL REG RESERVED
WINDOW/FRAME CONTROL REGISTERS
0
1
2
3
4
5
16 CONFIG HATCH WIND. SHDW COLOR PAGE HOR. DELAY
SPECIAL CONTROL REGISTERS
ADDRESS
BIT
7 6543
ROW
1 01 DD
COLUMN 0 0 X D D
COLUMN 0 1 X D D
X: don’t care
FORMAT
21 0
D D D a, b, c
D D D a, b
DD D c
D: valid data
CHARACTER ATTRIBUTE REGISTERS
14
0
11 12
18 19
31
15 WINDOW 1 ~ WINDOW 4 FRAME CRTL REG RESERVED
WINDOW/FRAME CONTROL REGISTERS
0
1
2
3
4
5
16 CONFIG HATCH WIND. SHDW COLOR PAGE HOR. DELAY
SPECIAL CONTROL REGISTERS
Figure 8. Address Bit Patterns for Attribute/Control Data
MEMORY MANAGEMENT
All the internal programmable area can be divided into
two parts including (1) Display Registers (2) Attribute/Control
Registers. Please refer to the following two figures for the
corresponding memory map.
MC141585
8
Figure 10. Memory Map of Attribute/Control Registers
Besides the font selection, there is 3-bit attribute associ-
ated with each symbol to identify its color and 3-bit to define
its background. Because of 3-bit attribute, each character
can select any color out of 8 independently on the same row.
as well as background. Every data row associate with one
attribute register, which locate at coln 30 of their respective
MOTOROLA
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