MC145173 查看數據表（PDF） - Motorola => Freescale

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MC145173

Dual-Band PLL Frequency Synthesizer with ADC and Frequency Counter

Motorola => Freescale 

PIN DESCRIPTIONS

DIGITAL INTERFACE PINS

Din

Serial Data Input (Pin 3)

The bit stream begins with the most significant bit (MSB)

and is shifted in on the low–to–high transition of CLK. The bit

pattern is 1 byte (8 bits) long to access the C register, 2 bytes

(16 bits) to access the N register, or 3 bytes (24 bits) to ac-

cess the R register. (See Table 1.) The values in the C, N,

and R registers do not change during shifting because the

transfer of data to the registers is controlled by ENB.

The bit stream needs neither address nor steering bits due

to the innovative BitGrabber registers. Therefore, all bits in

the stream are available to be data for the three registers.

Random access of any register is provided (i.e., the registers

may be accessed in any sequence). Data is retained in the

registers over a supply range of 4.5 to 5.5 V. The formats are

shown in Figures 17, 18, and 20.

Din typically switches near 45% of VDD for good noise im-

munity. This input can be directly interfaced to CMOS de-

vices with outputs guaranteed to switch near rail–to–rail.

When interfacing to NMOS or TTL devices, either a level

shifter (MC74HC14A, MC14504B) or pull–up resistor of 1 to

10 kΩ must be used. Parameters to consider when sizing the

resistor are worst–case IOL of the driving device, maximum

tolerable power consumption, and maximum data rate.

Table 1Write–Only Registers

(MSBs are shifted in first, C0, N0, and R0 are the LSBs)

Number

of Clocks

Accessed

Register

Bit

Nomenclature

8

16

24

Other Values ≤ 32

Values > 32

C Register

N Register

R Register

Not Allowed

Not Allowed

C7, C6, C5, . . ., C0

N15, N14, N13, . . ., N0

R23, R22, R21, . . ., R0

Table 2Read–Only Registers

(MSBs are shifted out first; A7 and F23 are the MSBs)

Number

of Clocks

Register

Bit

Nomenclature

8, 9, or 16

A Register

A7, A6, A5, . . ., A0, A#

24

F Register

F23, F22, F21, . . ., F0

CLK

Serial Data Clock Input (Pin 4)

Low–to–high transitions on Clock shift bits available at Din,

while high–to–low transitions shift bits from Dout. The chip’s

24–1/2–stage shift register is static, allowing clock rates

down to dc in a continuous or intermittent mode.

Eight clock cycles are required to access the C register.

Sixteen clock cycles are needed for the N register. 24 cycles

are used to access the R register. (See Table 1 and Figures

17, 18, and 20.)

The A register is read using 8, 9, or 16 clock cycles. The F

register is read using 24 clocks. (See Table 2 and Figures 21

and 22.)

CLK typically switches near 45% of VDD and has a

Schmitt–triggered input buffer. See the last paragraph of Din

for more information.

NOTE

To guarantee proper operation of the power–on

reset (POR) circuit, the CLK pin must be held at

the potential of either the VSS or VDD pin during

power up. That is, the CLK input should not be

floated or toggled while the VDD pin is ramping

from 0 to at least 4.5 V. If control of the CLK pin is

not practical during power up, then the RST bit in

the R Register must be utilized. See the R Regis-

ter Bits section.

ENB

Active–Low Enable Input (Pin 2)

This pin is used to activate the serial interface to allow the

transfer of data to/from the device. When ENB is in an inac-

tive high state, shifting is inhibited, Dout is forced to the high–

impedance state, and the port is held in the initialized state.

To transfer data to and from the device, ENB (which must

start inactive high) is taken low, a serial transfer is made via

Din, Dout, and CLK, and ENB is taken back high. The low–to–

high transition on ENB transfers data to the C, N, or R write–

only registers depending on the data stream length per

Table 1.

To minimize standby current, ENB must be high.

CAUTION

Transitions on ENB must not be attempted while

CLK is high. This puts the device out of synchro-

nization with the microcontroller. Resynchroniza-

tion occurs when ENB is high and CLK is low.

This input is also Schmitt–triggered and switches near

45% of VDD, thereby minimizing the chance of loading erro-

neous data into the registers. See the last paragraph of Din

for more information.

Dout

Three–State Serial Data Output (Pin 5)

Data is transferred out of the 24–1/2 stage shift register

through Dout on the high–to–low transition of CLK. The bit

stream begins with the MSB. The bit pattern is 1 byte, 9 bits,

or 2 bytes long to read the A register. The F register’s data is

contained in 3 bytes. (See Table 2.)

Before the A register can be read, the Read A bit must be

set in the C register. Likewise, the Read F bit must be set to

read the F register.

To minimize supply current during the standby state, the

Dout pin should not be floated. A pull–down resistor to VSS or

pull–up resistor to VDD should be used. The value can be

50 kΩ to 100 kΩ.

GENERAL–PURPOSE DIGITAL I/O PINS

Input C

Digital Input (Pin 7)

Input C is a general–purpose digital input which may be

used for MCU port expansion. The state of this input is indi-

cated by the In C bit in the A register. (See Figure 21.)

MC145173

8

MOTOROLA

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