MC14557BDW 查看數據表（PDF） - Motorola => Freescale
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MC14557BDW Datasheet PDF : 6 Pages
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ÎÎÎÎSÎÎÎÎWIÎÎÎÎTCHÎÎÎÎINGÎÎÎÎCHÎÎÎÎARÎÎÎÎAChCaÎÎÎÎTrEacRtÎÎÎÎeISriTsÎÎÎÎtIiCcSÎÎÎÎ* (CÎÎÎÎL=5ÎÎÎÎ0pFÎÎÎÎ,TAÎÎÎÎ=2ÎÎÎÎ5_CÎÎÎÎ)SymÎÎÎÎbolÎÎÎÎÎÎÎÎVÎÎÎÎDDÎÎÎÎÎÎÎÎÎÎÎÎMinÎÎÎÎÎÎÎÎTÎÎÎÎypÎÎÎÎ# ÎÎÎÎÎÎÎÎMaxÎÎÎÎÎÎÎÎUÎÎÎÎnitÎÎÎÎ
Rise and Fall Time, Q or Q Output
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
tTLH,
ns
tTHL
5
—
100
200
10
—
50
100
15
—
40
80
Propagation Delay, Clock or CE to Q or Q
tPLH, tPHL = (1.7 ns/pF) CL + 215 ns
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns
tPLH, tPHL = (0.5 ns/pF) CL + 65 ns
tPLH,
ns
tPHL
5
—
300
600
10
—
130
260
15
—
90
180
Propagation Delay, Reset to Q or Q
tPLH, tPHL = (1.7 ns/pF) CL + 215 ns
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns
tPLH, tPHL = (0.5 ns/pF) CL + 70 ns
tPLH,
ns
tPHL
5
—
300
600
10
—
130
260
15
—
95
190
Pulse Width, Clock
tWH(cl)
5
200
95
10
100
45
—
ns
—
15
75
35
—
Pulse Width, Reset
tWH(rst)
5
10
15
300
150
140
70
100
50
—
ns
—
—
Clock Frequency (50% Duty Cycle)
fcl
5
—
3.0
1.7
MHz
10
—
7.5
5.0
15
—
13.0
6.7
Setup Time, A or B to Clock or CE
Worst case condition: L1 = L2 = L4 = L8 =
L16 = L32 = VSS (Register Length = 1)
tsu
ns
5
700
350
—
10
290
130
—
15
145
85
—
Best case condition: L32 = VDD, L1 through L16 =
Don’t Care (Any register length from 33 to 64)
5
400
45
—
10
165
5
—
15
60
0
—
Hold Time, Clock or CE to A or B
Best case condition: L1 = L2 = L4 = L8 = L16 =
L32 = VSS (Register Length = 1)
th
ns
5
200
– 150
—
10
100
– 60
—
15
10
– 50
—
Worst case condition: L32 = VDD, L1 through L16 =
Don’t Care (Any register length from 33 to 64)
5
400
50
—
10
185
25
—
15
85
22
—
Rise and Fall Time, Clock
tr,
5
tf
10
15
—
No Limit
Rise and Fall Time, Reset or CE
tr,
5
—
—
15
µs
tf
10
—
—
5
15
—
—
4
Removal Time, Reset to Clock or CE
trem
5
160
80
10
80
40
15
70
35
—
ns
—
—
* The formulas given are for the typical characteristics only at 25_C.
# Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
TIMING DIAGRAM
VDD
50%
CLOCK
tWH(cl)
VSS
1/fcl
VDD
50%
A INPUT
tsu
th
trem
VSS
VDD
50%
RESET
1–bit length:
VSS
tTLH
tTHL
PWR
90%
VOH
CE = 0
50%
A/B = 1
Q
10%
L1 = L2 = L4 = L8 = L16 = L32 = 0 tPLH
tPHL
tPHL
VOL
MOTOROLA CMOS LOGIC DATA
MC14557B
3
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