CDP6805E2CE 查看數據表（PDF） - InnovASIC, Inc

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CDP6805E2CE

Microprocessor Unit

InnovASIC, Inc 

IA6805E2

Microprocessor Unit

Data Sheet

As of Production Version 00

Timer:

The MPU contains a single 8-bit software programmable counter driven by a 7-bit software

programmable prescaler. The counter may be loaded under program control and decrements

to zero. When the counter decrements to zero, the timer interrupt request bit in the timer

control register (TCR7) is set. Figure 13 shows a block diagram of the timer. If the timer

mask bit (TCR6) and the interrupt mask bit (I) of the condition code register are cleared, an

interrupt request is generated. After completion of the current instruction, the current state

of the machine is pushed onto the stack. The timer interrupt vector address is then fetched

from locations $1FF8 and $1FF9 and the interrupt routine is executed, unless the MPU was

in the WAIT mode in which case the interrupt vector address in locations $1FF6 and $1FF7

is fetched. Power-On-Reset causes the counter to set to $FF.

NOTE: 1. Prescaler and counter are clocked on the falling edge of the internal

clock (AS) or external input.

2. Counter is written to during Data Strobe (DS) and counts down continuously.

TIMER

(PIN 37)

INTERNAL

CLOCK

TIMER_n

EXT

CLK

2 - TO - 1

MUX

ENABLE /

DISABLE_n

INT

CLK

INTERNAL_n / EXTERNAL

PRESCALER

(7 BITS)

COUNTER

(8 BITS)

INTERRUPT

CONTROL

READ WRITE

INTERRUPT

TCR4 TCR5

TCR3 TCR2 TCR1 TCR0

SETTING TCR3 CLEARS

PRESCALER TO ÷ 1

SOFTWARE FUNCTIONS

Figure 13. Timer Block Diagram

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