MC33340 查看數據表（PDF） - ON Semiconductor
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MC33340 Datasheet PDF : 16 Pages
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MC33340, MC33342
1.6
Vmax
70
−DV
dV
1.5
dt
60
Tmax
1.4
50
1.3
40
Voltage
1.2
30
Temperature
1.1
20
Relative Pressure
1.0
10
0
40
80
120
160
CHARGE INPUT PERCENT OF CAPACITY
Figure 9. Typical Charge Characteristics for NiCd and NiMh Batteries
OPERATING DESCRIPTION
The MC33340/342 starts up in the fast charge mode when
power is applied to VCC. A change to the trickle mode can
occur as a result of three possible conditions. The first is if
the Vsen input voltage is above 2.0 V or below 1.0 V. Above
2.0 V indicates that the battery pack is open or disconnected,
while below 1.0 V indicates the possibility of a shorted or
defective cell. The second condition is when the
MC33340/342 detects a fully charged battery by measuring
a negative slope in battery voltage. The MC33340/342
recognize a negative voltage slope after the preset holdoff
time (thold) has elapsed during a fast charge cycle. This
indicates that the battery pack is fully charged. The third
condition is either due to the battery pack being out of a
programmed temperature range, or that the preset timer
period has been exceeded.
There are three conditions that will cause the controller to
return from trickle to fast charge mode. The first is if the Vsen
input voltage moved to within the 1.0 to 2.0 V range from
initially being either too high or too low. The second is if the
battery pack temperature moved to within the programmed
temperature range, but only from initially being too cold.
Third is by cycling VCC off and then back on causing the
internal logic to reset. A concise description of the major
circuit blocks is given below.
Negative Slope Voltage Detection
A representative block diagram of the negative slope
voltage detector is shown in Figure 10. It includes a
Synchronous Voltage to Frequency Converter, a Sample
Timer, and a Ratchet Counter. The Vsen pin is the input for
the Voltage to Frequency Converter (VFC), and it connects
to the rechargeable battery pack terminals through a
resistive voltage divider. The input has an impedance of
approximately 6.0 MW and a maximum voltage range of
−1.0 V to VCC + 0.6 V or 0 V to 10 V, whichever is lower.
The 10 V upper limit is set by an internal zener clamp that
provides protection in the event of an electrostatic discharge.
The VFC is a charge−balanced synchronous type which
generates output pulses at a rate of FV = Vsen (24 kHz).
The Sample Timer circuit provides a 95 kHz system clock
signal (SCK) to the VFC. This signal synchronizes the FV
output to the other Sample Timer outputs used within the
detector. At 1.38 second intervals the Vsen Gate output goes
low for a 33 ms period. This output is used to momentarily
interrupt the external charging power source so that a precise
voltage measurement can be taken. As the Vsen Gate goes
low, the internal Preset control line is driven high for 11 ms.
During this time, the battery voltage at the Vsen input is
allowed to stabilize and the previous FV count is preloaded.
At the Preset high−to−low transition, the Convert line goes
high for 22 ms. This gates the FV pulses into the ratchet
counter for a comparison to the preloaded count. Since the
Convert time is derived from the same clock that controls the
VFC, the number of FV pulses is independent of the clock
frequency. If the new sample has more counts than were
preloaded, it becomes the new peak count and the cycle is
repeated 1.38 seconds later. If the new sample has two fewer
counts, a less than peak voltage event has occurred, and a
register is initialized. If two successive less than peak
voltage events occur, the −DV ‘AND’ gate output goes high
and the Fast/Trickle output is latched in a low state,
signifying that the battery pack has reached full charge
status.
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