MC33883 查看數據表（PDF） - Motorola => Freescale

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MC33883

Full Bridge Pre-Driver

Motorola => Freescale 

DEVICE DESCRIPTION

Driver Supply

The High Side(HS) Driver is supplied from the internal

charge pump buffered at CP_OUT.

The low-drop regulator provides approx. 4mA (fPWM = 50KHz)

per HS gate. In case of the full bridge that means approximately

16mA, 8.0 mA for the high side and 8.0 mA for the low side.

(Note: The average current required to switch a gate with a

frequency of 100KHz is:

Average Current (Charge Pump) for PWM Frq. (fPWM)

ICP = Qg*fPWM = 80nC*100 kHz = 8.0mA

A full bridge application switch only one high side and one

low side at the same time.)

External capacitors on Charge Pump and on Linear Regula-

tor are necessary to supply high peak current absorbed dur-

ing switching. The Low Side Driver is supplied from built in

low drop regulator.

Gate Protection

The low side gate is protected by the internal linear regula-

tor, which guarantees that VGATE_LS does not exceed the

maximum VGS. Especially when working with the charge

pump the voltage at POS_HS can be up to 65V. The high

side gate is clamped internally, in order to avoid a VGS ex-

ceeding 18V.

The Gate protection does not include a Flyback Voltage

Clamp that protects the driver and the external FET from a

Flyback voltage that can appear when driving inductive

load.This Flyback voltage can reach high negative voltage

values and needs to be clamped externally.

Figure 4: Gate Protection & Flyback Voltage Clamp

Vgs_ls

Vgs_hs

IN Output OUT

Driver

M1

GATE_HS

G_LOW

SRC_HS

G_LOW

IN Output OUT

Driver

Dcl

L1

M2

GATE_LS

VCC

VGS < 14 V

under all

conditions

Inductive

Flyback Voltage

Clamp

(Gate = VCC, or Gate = Gnd) the function of the remaining output

driver stages is not affected. All output drivers are short circuit

protected against short circuits to ground.

Logic Inputs

Logic Input Voltage Range:

Absolute Max :

-0.3V ... 10V

Wake Up Function: (G_EN)

4.5V ... VCC2

During Wake-Up the logic is supplied from the G_EN pin.

Low Drop Linear Regulator

The low drop linear regulator provides the 5.0V for the logic

section of the driver, the Vgs_ls buffered at LR_OUT and the

+14.5V for the charge pump, which generates the Vgs_hs.

The low drop linear regulator provides 4.0mA average current

per driver stage. If typically VCC2 exceeds 15.0V the output is

limited to 14.5Vtyp.

Charge Pump

The charge pump generates the high side driver supply volt-

age (VGS_HS), buffered at CP_OUT.

Vgs_hs = VCC + VLR_OUT - 2V.

The average output current is ICP = 4.0 mA (fPWM = 50 KHz)

per output driver.

The charge pump charges an external storage capacitor,

which provides the peak switching current to the high side

output drivers.

N.B. In some applications a large dV/dt at Pin C2 due to

sudden changes at VCC can cause a large peak currents

flowing through Pin C1.

Positive transitions at Pin C2 ;mimimum peak current :

Ic1min = 2.0A

tc1min = 600ns (see Figure 5:for peak description)

Negative transitions at Pin C2; maximum peak current :

Ic1max = 2.0A

tc1max = 600ns (see Figure 5 for peak description)

Current sourced by Pin C1 during a large dV/dt will result in

a negative voltage at Pin 13; negative transitions at Pin C2;

minimum peak voltage:

Vc1min = -1.5V

tc1max = 600ns (see Figure 5:for peak description)

TMOS Failure Protection

All output driver stages are protected against TMOS failure

conditions. If one of the external power FETs is destroyed

MC33883

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