MC33999 查看數據表（PDF） - Motorola => Freescale

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MC33999

16-Output Switch with SPI and PWM Control

Motorola => Freescale 

Freescale Semiconductor, Inc.

MC68HCXX

Microcontroller

Shift Register

Parallel

Ports

MOSI

MISO

SCLK

PWM1

PWM2

33999

SI

SO

SCLK

CS

PWM

RST

33999

SI

SO

SCLK

CS

PWM

RST

Figure 5. Parallel Inputs SI Control

FUNCTIONAL PIN DESCRIPTION

Chip Select (CS) Pin

The system MCU selects which 33999 is to be

communicated with through the use of the Chip Select (CS) pin.

When the CS pin is in a logic low state, data can be transferred

from the MCU to the 33999 and vise versa. Clocked-in data

from the MCU is transferred from the 33999 Shift register and

latched into the power outputs on the rising edge of the CS

signal. On the falling edge of the CS signal, output fault status

information is transferred from the Power Outputs Status

register into the device’s SO Shift register. The SO pin output

driver is enabled when CS is low, allowing information to be

transferred from the 33999 to the MCU. To avoid any spurious

data, it is essential the high-to-low transition of the CS signal

occur only when SCLK is in a logic low state.

System Clock (SCLK) Pin

The System Clock (SCLK) pin clocks the Internal Shift

register of the 33999. The Serial Input (SI) pin accepts data into

the Input Shift register on the falling edge of the SCLK signal

while the Serial Output (SO) pin shifts data information out of

the Shift register on the rising edge of the SCLK signal. False

clocking of the Shift register must be avoided to guarantee

validity of data. It is essential the SCLK pin be in a logic low

state whenever the Chip Select (CS) pin makes any transition.

For this reason, it is recommended, though not necessary, that

the SCLK pin is commanded to a low logic state as long as the

device is not accessed (CS in logic high state). When the CS is

in a logic high state, any signal at the SCLK and SI pins is

ignored and the SO is tri-stated (high impedance).

Serial Input (SI) Pin

The Serial Input (SI) pin is used to enter one of seven serial

instructions into the 33999. SI SPI bits are latched into the Input

Shift register on each falling edge of SCLK. The Shift register is

full after 24 bits of information are entered. The 33999 operates

on the command word on the rising edge of CS. To preserve

data integrity, exercise care to not transition SI as the SCLK

transitions from high-to-low state (see Figure 2, page 8).

Serial Output (SO) Pin

The Serial Output (SO) pin transfers fault status data from

the 33999 to the MCU. The SO pin remains tri-state until the CS

pin transitions to a logic low state. All faults on the 33999 are

reported to the MCU as logic [1]. Conversely, normal operating

outputs with nonfaulted loads are reported as logic [0]. On the

falling edge of the CS signal, output fault status information is

transferred from the Power Outputs Status register into the

device’s SO Shift register. The first eight positive transitions of

SCLK will provide Any Fault (bit 23), Overvoltage Fault (bit 22),

followed by six logic [0]s (bits 21 to 16). The next 16 successive

positive clock provides fault status for output 15 to output 0. The

SI/SO shifting of data follows a first-in, first-out protocol with

33999

10

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