MC34700EP_R2 查看數據表（PDF） - Freescale Semiconductor

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MC34700EP_R2

9.0 to 18 V, Quad Output, Integrated MOSFET Power Supply

Freescale Semiconductor 

Table 3. 34700 Pin Definitions (continued)

PIN CONNECTIONS

FUNCTIONAL PIN DESCRIPTIONS

Pin Name

Pin Description

13

EN3 This input enables buck regulator #3. Asserting EN3 high turns on DC/DC #3. The internal control logic remains active

as long as VIN is present.

14 EN_LDO This input enables the LDO. Asserting EN_LDO high turns on the LDO. The internal control logic remains active as long

as VIN is present.

15

FB3 DC/DC #3’s error amplifier inverting input. Connect the required compensation network and feedback network to this

terminal as appropriate.

16 COMP3 Buck regulator #3’s compensation output. COMP3 is connected to DC/DC #3’s error amplifier’s output. Connect the

required external compensation network between the COMP3 pin and the FB3 pin.

17

BST3 Buck regulator #3’s bootstrap capacitor input. Connect a capacitor between the BST3 and SW3 pin of DC/DC #3 to

enhance the gate of the high side MOSFET during switching.

18

VIN3 Buck regulator #3’s power input voltage. VIN3 is connected to the drain of the DC/DC #3’s high side MOSFET. Local

bypass capacitors are recommended.

19

SW3 Buck regulator #3’s switching node. SW3 is connected to source of the high side and the drain of the low side MOSFET.

Connect this pin to the output inductor.

20

GND3 Buck regulator #3’s power ground. GND3 is connected to the source of DC/DC #3’s low side MOSFET. Connect this pin

to the DC/DC #3’s power return path.

21 LDO_FB LDO error amplifier inverting input. Connect the appropriate output voltage feedback resistor divider to this pin.

22

LDO LDO regulator output. Connect this pin to the feedback resistor divider and output capacitor.

23 LDO_VIN LDO’s power input voltage. LDO_VIN is connected to the drain of the linear regulator’s pass device. Local bypass

capacitors are recommended.

24

VIN IC supply voltage input. This pin should be de-coupled from the buck regulator’s power input voltages (VIN1, VIN2, VIN3).

Filtering is required for proper device operation.

25 VGREG This is the output of an internal linear regulator which is used to supply the gate drivers. The VGREG linear regulator is

driven from the input supply voltage VIN, and it’s output is also used to drive the gates of the low side MOSFETs of

regulators DC/DC #2 and DC/DC #3, as well as the LDO. Connect this pin to a low ESR, 1.0 μF bypass capacitor.

26

VDDI Internal regulator output used to supply the internal logic and analog blocks. VDDI is driven from the gate drive supply

voltage, VGREG. Connect this pin to a 1.0 μF, low ESR decoupling filter capacitor.

27 PGOOD Status signal used to indicate that all the regulators’ output voltages are good. Upon a fault occurrence, this output signal

goes low. PGOOD is an open drain output, and must be pulled up by an external resistor to a supply voltage suitable for

I/O.

28

AGND Analog ground of the IC. Internal analog and logic signals are referenced to this pin.

29 VOUT1 DC/DC #1’s shunt input. VOUT1 is connected to a discharge MOSFET. This MOSFET is used to discharge the output of

DC/DC1 when there is a fault condition, such as thermal shutdown or a short circuit. It is also used to provide a pre-load

to maintain a minimum duty. Connect this pin to the output of DC/DC #1.

30

FB1 DC/DC #1’s error amplifier inverting input. Connect the required compensation network and feedback network to this

terminal as appropriate.

31 COMP1 Buck regulator #1’s compensation output. COMP1 is connected to DC/DC #1’s error amplifier’s output. Connect the

required external compensation network between the COMP1 pin and the FB1 pin.

33

AGND Thermal pad for heat transfer. Connect the thermal pad to the analog ground.

Analog Integrated Circuit Device Data

Freescale Semiconductor

34700

9

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