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MC34701

1.5A Switch-Mode Power Supply with Linear Regulator

Freescale Semiconductor 

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 4. DYNAMIC ELECTRICAL CHARACTERISTICS (continued)

Characteristics noted under conditions -40°C ≤ TA ≤ 85°C unless otherwise noted. Input voltages VIN1 = VIN2 = 3.3V using

the typical application circuit (see Figures 33), unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

BOOST REGULATOR

Boost Regulator MOSFET Maximum ON Time(21)

Boost Regulator Control Loop Propagation Delay(21)

Boost Switching Node VBD Rise Time(21)

IBST = 20mA

Boost Switching Node VBD Fall Time(21)

IBST = 20mA

LINEAR REGULATOR (LDO)

tON

–

24

–

µs

tBST_PD

–

50

–

ns

tB_RISE

ns

–

5.0

tB_FALL

ns

–

3.0

–

Fault Condition Timeout

Retry Timer Cycle

RESET MONITOR (RST)

tFAULT

7.0

10

15

ms

tRET

70

100

150

ms

Monitoring LFB Pin Delay

Monitoring INV Pin Delay

SCA, SCL PIN, I2C BUS (STANDARD)

tD_RST_LFB

12

–

28

µs

tD_RST_INV

12

–

28

µs

SCL Clock Frequency(21)

fSCL

–

–

100

kHz

Bus Free Time Between a STOP and a START Condition(21)

tBUF

4.7

–

–

µs

Hold Time (Repeated) START Condition (After this period, the first clock

tHD-STA

pulse is generated.)(21)

4.0

–

µs

–

Low Period of the SCL Clock(21)

tLOW

4.7

–

–

µs

High Period of the SCL Clock(21)

tHIGH

4.0

–

–

µs

SDA Fall Time from VIH_MAX to VIL_MIN, Bus Capacitance 10pF to 400pF,

tF

3.0mA Sink Current(21), (23)

ns

–

–

250

Setup Time for a Repeated START Condition(21)

tSU-STA

4.7

–

–

µs

Data Hold Time for I2C Bus Devices(21), (22)

tHD-DAT

0.0

–

–

µs

Data Setup Time(21)

tSU-DAT

250

–

–

ns

Setup Time for STOP Condition(21)

tSU-STO

4.0

–

–

µs

Capacitive Load for Each Bus Line(21)

CB

–

–

400

pF

Notes

21. Design information only. This parameter is not production tested.

22. The device provides an internal hold time of at least 300ns for the SDA signal (refer to the VIH_MIN of the SCL signal) to bridge the

undefined region of the falling edge of SCL.

23. VIH is high level voltage on I2C bus lines and VIL is low level voltage on I2C bus lines

Analog Integrated Circuit Device Data

Freescale Semiconductor

34701

13

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