MC44817BD 查看數據表（PDF） - Motorola => Freescale
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MC44817BD Datasheet PDF : 8 Pages
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MC44817/17B
ELECTRICAL CHARACTERISTICS (VCC1 = 5.0 V, VCC2 = 33 V, VCC3 = 12 V, TA = 25°C, unless otherwise noted.)
Characteristic
Pin
Min
Typ
Max
VCC1 Supply Voltage Range
VCC1 Supply Current (VCC1 = 5.0 V)
VCC2 Supply Voltage Range
VCC2 Supply Current (Output Open)
Band Buffer Leakage Current when “Off” at 12 V
7
7
6
6
10–13
4.5
5.0
5.5
–
37
50
25
–
37
–
1.5
3.5
–
0.01
1.0
Band Buffer Saturation Voltage when “On” at 30 mA
10–13
–
0.15
0.3
Band Buffer Saturation Voltage when “On” at 40 mA
only for 0° to 80°C
10–13
–
0.2
0.5
Data/Clock/Enable Current at 0 V
1, 2, 16
–10
–
0
Data/Clock/Enable Current at 5.0 V
1, 2, 16
0
–
1.0
Data/Clock/Enable Input Voltage Low
1, 2, 16
–
–
1.5
Data/Clock/Enable Input Voltage High
1, 2, 16
3.0
–
–
Clock Frequency Range
2
–
–
100
Oscillator Frequency Range
3
3.15
3.2
4.05
Operational Amplifier Internal Reference Voltage
–
2.0
2.75
3.2
Operational Amplifier Input Current
4
–15
0
15
DC Open Loop Voltage Gain
–
100
250
–
Gain Bandwidth Product (CL = 1.0 nF)
Vout Low, Sinking 50 µA
Vout High, Sourcing 10 µA, VCC2 – Vout
Phase Comparator Tri–State Current
–
0.3
–
–
5
–
0.2
0.4
5
–
0.2
0.5
4
–15
0
15
Charge Pump High Current of Phase Comparator
4
30
50
85
Charge Pump Low Current of Phase Comparator
4
10
15
30
VCC3 Supply Voltage Range
VCC3 Supply Current
All Buffers “Off”
One Buffer “On” when Open
One Buffer “On” at 40 mA
14
VCC1
–
14.4
14
–
0.2
0.5
–
8.0
13
–
48
53
Unit
V
mA
V
mA
µA
V
V
µA
µA
V
V
kHz
MHz
V
nA
V/V
MHz
V
V
nA
µA
µA
V
mA
Data Format and Bus Receiver
The circuit is controlled by a 3–wire bus via Data (DA),
Clock (CL), and Enable (EN) inputs. The Data and Clock
inputs may be shared with other inputs on the IIC–Bus while
the Enable is a separate signal. The circuit is compatible with
18 and 19 bit data transmission and also has a mode for
34 bit transmission for test and additional features.
The 3–wire bus receiver receives data for the internal shift
register after the positive going edge of the EN–signal. The
data is transmitted to the band buffers on the negative going
edge of the clock pulse 4 (signal DTB1).
18 and 19 Bit Data Transmission
The programmable divider may receive 14 bit (18 bit
transmission) or 15 bit (19 bit transmission). The data is
transmitted to the programmable divider (latches A) on the
negative going edge of clock pulse 19 or on the negative
edge of the EN–signal if EN goes down after the 18th clock
pulse (signal DTF). If the programmable divider receives
14 bit, its MSB (bit N14) is internally reset. The reset pulse is
generated only if EN goes negative after the 18th clock pulse
(signal RL).
34 Bit Data Transmission
(For Test and Additional Features)
In the test mode, the programmable divider receives 15 bit
and the data is transferred to latches A on the negative edge
of clock pulse 19 (signal DTF). The information for test is
received on clock pulses 20 to 26 and transmitted to the
latches on the negative edge of pulse 34 (signal DTB2).
These latches have a power–on reset. The power–on reset
sets the programmable divider to a counting ratio of 256 or
higher and resets the corresponding latches to the test bits
T0 to T6 (signal POR). The bus receiver is not disturbed if the
data format is wrong. Useless bits are ignored. If for example
the Enable signal goes low after the clock pulse 9, bits one to
four are accepted as valid buffer information and the other
bits are ignored. If more than 34 bits are received, bit 35 and
the following are ignored.
Lock Detector
The lock–detector output is low in lock. The output goes
immediately high when an unlock condition is detected. The
output goes low again when the loop is in lock during a
complete period of the reference frequency.
MOTOROLA ANALOG IC DEVICE DATA
3
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