56F8002 查看數據表（PDF） - Freescale Semiconductor

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56F8002

Digital Signal Controller

Freescale Semiconductor 

Block Diagram

2 Block Diagram

Figure 1shows a top-level block diagram of the MC56F8006/MC56F8002 digital signal controller. Package options for this

family are described later in this document. Italics indicate a 56F8002 device parameter.

PWM

6 PWM Outputs

3

Fault Inputs

programmable

delay block

24 Total

ADCA

PGA/ADC

ADCB

2

CMP0 CMP

or

2

GPIOD

CMP1

2

CMP2

Note: All pins

40

are muxed with

other peripheral

pins.

4

GPIO are

muxed with

all other func

pins.

Dual GP Timer

RESET

VDD VSS VDDA VSSA

4

3

3

Program Controller

and Hardware

Looping Unit

PAB

PDB

CDBR

CDBW

JTAG/EOnCE

Digital Reg Analog Reg

Port or GPIOD

16-Bit 56800E Core

Low-Voltage

Supervisor

PMC

Address

Generation Unit

Data ALU 16 x 16 + 36 → 36-Bit MAC

Three 16-bit Input Registers

Four 36-bit Accumulators

Bit

Manipulation

Unit

Memory

Flash Memory

16 Kbytes flash

12 Kbytes flash

Unified Data /

Program RAM

2KB

XDB2

XAB1

XAB2

PAB

PDB

CDBR

CDBW

R/W Control

System Bus

Control

PIT

IPBus Bridge

Power

Management

Controller

RTC

SPI SCI

I2C

4

2

2

Interrupt

COP/

Controller

Watchdog

System

Integration

Module

Figure 1. MC56F8006/MC56F8002 Block Diagram

Clock ROSC

Generator* OSC

2

Crystal

Oscillator

3 Overview

3.1 56F8006/56F8002 Features

3.1.1 Core

• Efficient 16-bit 56800E family digital signal controller (DSC) engine with dual Harvard architecture

• As many as 32 million instructions per second (MIPS) at 32 MHz core frequency

• 155 basic instructions in conjunction with up to 20 address modes

• Single-cycle 16 × 16-bit parallel multiplier-accumulator (MAC)

• Four 36-bit accumulators, including extension bits

• 32-bit arithmetic and logic multi-bit shifter

MC56F8006/MC56F8002 Digital Signal Controller, Rev. 2

4

Freescale Semiconductor

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