56F8165(2007) 查看數據表（PDF） - Freescale Semiconductor

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产品描述 (功能)

生产厂家

56F8165
(Rev.:2007)

16-bit Digital Signal Controllers

Freescale Semiconductor 

56F8365/56F8165 Features

Part 1 Overview

1.1 56F8365/56F8165 Features

1.1.1 Core

• Efficient 16-bit 56800E family controller engine with dual Harvard architecture

• Up to 60 Million Instructions Per Second (MIPS) at 60MHz core frequency

• Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)

• Four 36-bit accumulators, including extension bits

• Arithmetic and logic multi-bit shifter

• Parallel instruction set with unique DSP addressing modes

• Hardware DO and REP loops

• Three internal address buses

• Four internal data buses

• Instruction set supports both DSP and controller functions

• Controller-style addressing modes and instructions for compact code

• Efficient C compiler and local variable support

• Software subroutine and interrupt stack with depth limited only by memory

• JTAG/EOnCE debug programming interface

1.1.2 Differences Between Devices

Table 1-1 outlines the key differences between the 56F8365 and 56F8165 devices.

Table 1-1 Device Differences

Feature

56F8365

Guaranteed Speed

Program RAM

Data Flash

PWM

CAN

Quad Timer

Quadrature Decoder

Temperature Sensor

60MHz/60 MIPS

4KB

32KB

2x6

2

4

2x4

1

56F8165

40MHz/40MIPS

Not Available

Not Available

1x6

Not Available

2

1x4

Not Available

56F8365 Technical Data, Rev. 7

Freescale Semiconductor

5

Preliminary

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