MC68020FC16 查看數據表（PDF） - Motorola => Freescale

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MC68020FC16

MICROPROCESSORS USER’S MANUAL

Motorola => Freescale 

9/29/95

SECTION 1: OVERVIEW

UM Rev.1.0

TABLE OF CONTENTS (Continued)

Paragraph

Number

Title

Page

Number

3.12

Power Supply Connections .....................................................................3-7

3.13

Signal Summary......................................................................................3-8

4.1

4.2

4.3

4.3.1

4.3.2

Section 4

On-Chip Cache Memory

On-Chip Cache Organization and Operation ..........................................4-1

Cache Reset ...........................................................................................4-3

Cache Control .........................................................................................4-3

Cache Control Register (CACR) .........................................................4-3

Cache Address Register (CAAR) ........................................................4-4

5.1

5.1.1

5.1.2

5.1.3

5.1.4

5.1.5

5.1.6

5.1.7

5.2

5.2.1

5.2.2

5.2.3

5.2.4

5.2.5

5.2.6

5.2.7

5.3

5.3.1

5.3.2

5.3.3

5.4

5.4.1

5.4.1.1

5.4.1.2

5.4.1.3

5.4.2

5.4.3

5.5

5.5.1

Section 5

Bus Operation

Bus Transfer Signals...............................................................................5-1

Bus Control Signals .............................................................................5-2

Address Bus ........................................................................................ 5-3

Address Strobe ....................................................................................5-3

Data Bus.............................................................................................. 5-3

Data Strobe .........................................................................................5-4

Data Buffer Enable ..............................................................................5-4

Bus Cycle Termination Signals............................................................5-4

Data Transfer Mechanism.......................................................................5-5

Dynamic Bus Sizing ............................................................................5-5

Misaligned Operands...........................................................................5-14

Effects of Dynamic Bus Sizing and Operand Misalignment ................ 5-20

Address, Size, and Data Bus Relationships ........................................5-21

Cache Interactions ..............................................................................5-22

Bus Operation ..................................................................................... 5-24

Synchronous Operation with DSACK1/DSACK0 ............................... 5-24

Data Transfer Cycles ..............................................................................5-25

Read Cycle ..........................................................................................5-26

Write Cycle ..........................................................................................5-33

Read-Modify-Write Cycle.....................................................................5-39

CPU Space Cycles .................................................................................5-44

Interrupt Acknowledge Bus Cycles ......................................................5-45

Interrupt Acknowledge Cycle—Terminated Normally ...................... 5-45

Autovector Interrupt Acknowledge Cycle .........................................5-48

Spurious Interrupt Cycle ..................................................................5-48

Breakpoint Acknowledge Cycle ...........................................................5-50

Coprocessor Communication Cycles .................................................. 5-53

Bus Exception Control Cycles.................................................................5-53

Bus Errors ........................................................................................... 5-55

viii

M68020 USER’S MANUAL

MOTOROLA

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