MC68060 查看數據表（PDF） - Motorola => Freescale
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MC68060 Datasheet PDF : 10 Pages
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CACHE ORGANIZATION
The instruction and data caches are each organized as four-way set associative, with 16-byte lines. Each line
of data has associated with it an address tag and state information that shows the line’s validity. In the data
cache, the state information indicates whether the line is invalid, valid, or dirty.
CACHE COHERENCY
The MC68060 has the ability to watch, or snoop, the external bus during accesses by other bus masters,
maintaining coherency between the MC68060 caches and external memory systems. External bus cycles can
be flagged on the bus as snoopable or nonsnoopable. When an external cycle is marked as snoopable, the
bus snooper checks the caches and invalidates the matching data. Although the execution unit and the bus
snooper circuit have access to the on-chip caches, the snooper has priority over the execution unit.
BUS CONTROLLER
The bus is implemented as a nonmultiplexed, fully synchronous protocol that is clocked off the rising edge of
the input clock. It is compatible with an MC68040 bus. The bus controller operates concurrently with all other
functional units of the MC68060 to maximize system throughput. The timing of the bus is fully configurable to
match external memory requirements.
The CLKEN input is used on the MC68060 to enable to the clock edges on which the bus controller will
respond. By toggling the CLKEN pin, it is possible to operate the MC68060 on an external bus at 1/2 or 1/4
the speed of the processor clock.
Although the MC68060 bus is compatible with the MC68040, additional signals and protocols have been
added to simplify designs requiring very high bus speeds.
IEEE 1149.1 TEST
To aid in system diagnostics, the MC68060 includes dedicated user-accessible test logic that is fully compliant
with the IEEE 1149.1 standard for boundary scan testability, often referred to as Joint Test Action Group
(JTAG).
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MC68060 PRODUCT INFORMATION
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