MC68LC060 查看數據表（PDF） - Freescale Semiconductor

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MC68LC060

M68060 User’s Manual

Freescale Semiconductor 

6.1.3.4

6.1.4

6.2

6.3

6.3.1

6.3.2

6.4

6.4.1

6.4.2

6.5

6.5.1

6.5.2

6.5.3

6.6

6.6.1

6.6.1.1

6.6.1.2

6.6.2

6.6.2.1

6.6.2.2

6.6.3

6.6.3.1

6.6.3.2

6.6.4

6.6.4.1

6.6.4.2

6.6.5

6.6.5.1

6.6.5.2

6.6.6

6.6.6.1

6.6.6.2

6.6.7

6.6.7.1

6.6.7.2

6.7

7.1

7.2

7.3

7.4

7.5

7.6

Table of Contents

Accrued Exception Byte ........................................................................... 6-6

Floating-Point Instruction Address Register (FPIAR) ................................. 6-7

Floating-Point Data Formats and Data Types............................................... 6-7

Computational Accuracy ............................................................................. 6-11

Intermediate Result................................................................................... 6-12

Rounding the Result ................................................................................. 6-13

Postprocessing Operation........................................................................... 6-15

Underflow, Round, and Overflow.............................................................. 6-15

Conditional Testing ................................................................................... 6-16

Floating-Point Exceptions ........................................................................... 6-19

Unimplemented Floating-Point Instructions .............................................. 6-19

Unsupported Floating-Point Data Types................................................... 6-21

Unimplemented Effective Address Exception........................................... 6-22

Floating-Point Arithmetic Exceptions .......................................................... 6-22

Branch/Set on Unordered (BSUN)............................................................ 6-24

Trap Disabled Results (FPCR BSUN Bit Cleared) ................................. 6-24

Trap Enabled Results (FPCR BSUN Bit Set) ......................................... 6-24

Signaling Not-a-Number (SNAN) .............................................................. 6-25

Trap Disabled Results (FPCR SNAN Bit Cleared) ................................. 6-25

Trap Enabled Results (FPCR SNAN Bit Set) ......................................... 6-26

Operand Error........................................................................................... 6-26

Trap Disabled Results (FPCR OPERR Bit Cleared)............................... 6-27

Trap Enabled Results (FPCR OPERR Bit Set)....................................... 6-27

Overflow.................................................................................................... 6-28

Trap Disabled Results (FPCR OVFL Bit Cleared) .................................. 6-29

Trap Enabled Results (FPCR OVFL Bit Set) .......................................... 6-29

Underflow.................................................................................................. 6-30

Trap Disabled Results (FPCR UNFL Bit Cleared) .................................. 6-31

Trap Enabled Results (FPCR UNFL Bit Set) .......................................... 6-31

Divide-by-Zero .......................................................................................... 6-32

Trap Disabled Results (FPCR DZ Bit Cleared)....................................... 6-33

Trap Enabled Results (FPCR DZ Bit Set)............................................... 6-33

Inexact Result ........................................................................................... 6-33

Trap Disabled Results (FPCR INEX1 Bit and INEX2 Bit Cleared........... 6-34

Trap Enabled Results (Either FPCR INEX1 Bit or INEX2 Bit Set).......... 6-34

Floating-Point State Frames ....................................................................... 6-35

Section 7

Bus Operation

Bus Characteristics ....................................................................................... 7-1

Full-, Half-, and Quarter-Speed Bus Operation and BCLK ........................... 7-3

Acknowledge Termination Ignore State Capability ....................................... 7-4

Bus Control Register..................................................................................... 7-4

Data Transfer Mechanism............................................................................. 7-5

Misaligned Operands .................................................................................... 7-9

MOTOROLA

M68060 USER’S MANUAL

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