MC68HCL05P1DW 查看數據表（PDF） - Freescale Semiconductor

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MC68HCL05P1DW

HCMOS Microcontroller Unit

Freescale Semiconductor 

Freescale Semiconductor, Inc.

CORRECTIONS TO MC68HC05P1 Technical Data REV. 1

Corrections to MC68HC05P1 Technical Data REV. 1 are as follows:

1. Page 3-25, 3.5.2 WAIT Mode — Delete the following sentence from the first paragraph:

If the A/D converter is enabled, it is also active in WAIT mode.

2. Page 3-25, 3.5.2 WAIT Mode — Delete the second paragraph.

3. Page 6-9, 6.7 Timer during WAIT Mode — The first sentence should read as follows:

The internal clock halts during WAIT mode, but the capture/compare timer remains active.

4. Page 6-9, 6.8 Timer during STOP Mode —The second sentence should read as follows:

If IRQ is used to exit STOP mode, the timer resumes counting from the count value that was

present when STOP mode was entered.

5. Page 8-4, Table 8-4. DC Electrical Characteristics (VDD = 3.3 Vdc) — NOTE 2 at the

bottom of Table 8-4 should read as follows:

2. Run (operating) IDD and WAIT IDD measured using external square wave clock source

(fOSC = 2.1 MHz). All inputs 0.2 V from rail. No dc loads. Less than 50 pF on all outputs.

CL = 20 pF on OSC2.

6. Page 8-6, Figure 8-5. Maximum Supply Current vs Clock Frequency — Internal clock

frequency scale at bottom of VDD = 3.3 V 10% graph should read as follows:

0

250 kHz

500 kHz

750 kHz

1 MHz

MC68HC05P1AD/D

REV. 1

MOTOROLA

3

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