MC74LVX138(2014) 查看數據表（PDF） - ON Semiconductor

零件编号

产品描述 (功能)

生产厂家

MC74LVX138
(Rev.:2014)

3-to-8 Line Decoder With 5V−Tolerant Inputs

ON Semiconductor 

MC74LVX138

3-to-8 Line Decoder

With 5V−Tolerant Inputs

The MC74LVX138 is an advanced high speed CMOS 3−to−8 line

decoder. The inputs tolerate voltages up to 7.0 V, allowing the

interface of 5.0 V systems to 3.0 V systems.

When the device is enabled, three Binary Select inputs (A0 − A2)

determine which one of the outputs (O0 − O7) will go Low. When

enable input E3 is held Low or either E2 or E1 is held High, decoding

function is inhibited and all outputs go high. E3, E2, and E1 inputs are

provided to ease cascade connection and for use as an address decoder

for memory systems.

Features

• High Speed: tPD = 5.5 ns (Typ) at VCC = 3.3 V

• Low Power Dissipation: ICC = 4 mA (Max) at TA = 25 °C

• Power Down Protection Provided on Inputs

• Balanced Propagation Delays

• Low Noise: VOLP = 0.5 V (Max)

• Pin and Function Compatible with Other Standard Logic Families

• Latchup Performance Exceeds 300 mA

• ESD Performance:

Human Body Model > 2000 V;

Machine Model > 200 V

• These Devices are Pb−Free and are RoHS Compliant

© Semiconductor Components Industries, LLC, 2014

1

August, 2014 − Rev. 4

http://onsemi.com

SOIC−16

D SUFFIX

CASE 751B

TSSOP−16

DT SUFFIX

CASE 948F

PIN ASSIGNMENT

VCC O0 O1 O2 O3 O4 O5 O6

16 15 14 13 12 11 10 9

12345678

A0 A1 A2 E1 E2 E3 O7 GND

16−Lead (Top View)

PIN NAMES

Pins

A0−A2

E1−E2

E3

O0−O7

Function

Address Inputs

Enable Inputs

Enable Input

Outputs

MARKING DIAGRAMS

16

LVX138G

AWLYWW

1

SOIC−16

16

LVX

138

ALYWG

G

1

TSSOP−16

LVX138 = Specific Device Code

A

= Assembly Location

WL, L = Wafer Lot

Y

= Year

WW, W = Work Week

G or G = Pb−Free Package

(Note: Microdot may be in either location)

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 5 of this data sheet.

Publication Order Number:

MC74LVX138/D

Share Link: