M66009FP 查看數據表（PDF） - MITSUBISHI ELECTRIC

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M66009FP

8-BIT I/O EXPANDER WITH 5-BIT ADDRESS

MITSUBISHI ELECTRIC  

MITSUBISHI 〈DIGITAL ASSP〉

M66009FP

8-BIT I/O EXPANDER WITH 5-BIT ADDRESS

DATA SENDING/RECEIVING PROTOCOL AND OPERA-

TION PROCEDURE

The timing at which microcomputer communicates with

M66009 is as shown in the diagram below. When microcom-

puter accesses to M66009, it declares the start of access by

lowering pin EN status from “H” to “L”. It then sends data to

pins CLK and DI at the timing shown below. The access stops

as pin EN status rises from “L” to “H”. Given below is more de-

tailed explanation of data sending/receiving procedure:

(1) At EN fall edge, 8-bit parallel data that arrives at input/out-

put pins D0 thru D7 is loaded into shift register for serial

output.

(2) At CLK rise edge, data at pin DI is taken into serial input

shift register, and internal clock counter starts counting up.

(3) When 5-bit address is taken in, it is compared to address

set by pins A0 thru A4. If they are the same, acknowledge

bit “0” is output to pin DO synchronously with CLK 8T fall

edge.

(When the addresses are not the same, pin DO output

status stays at the “H” level.)

(4) When command bits C2, C1 and C0 are all “1”, operation

proceeds to (5) and (6) described below.

If any of these command bits are not “1” while the ad-

dresses are the same, pin DO output is fixed to “H” syn-

chronously with CLK 9T rise, and operation is halted until

EN rises. When EN rises, clock counter is reset, and

M66009 becomes ready to accept a next access.

(5) When the addresses are the same and the command bits

are all “1”, serial output operation starts. Eight-bit data

latched at step (1) as described above is output in series,

starting from the bit at pin D7, through pin DO synchro-

nously with the fall edges of CLK 9T thru 16T. No opera-

tion is performed for CLK inputs after 16T, except the

count up of CLK.

(6) When EN rises: Output pin DO status is fixed to “H”, and

only when clock counter has counted 16 CLK rise edges

(counter output =10H), the lower 8 bits of the 16-bit serial

data is sent to output latch synchronously with the EN rise

edge. The latched data is inverted in logic, and output to

pins D0 thru D7 in parallel. Clock counter is then reset,

completing one sequence.

(Note) If the clock counter output is not 10 H when EN rises,

data is not sent to output latch. Output pin DO is fixed

to “H”, clock counter is reset, and M66009 becomes

ready to accept a next access.

EN

CLK

1T 2T

6T 7T 8T 9T

15T 16T

DI

A4 A3 A2 A1 A0 C2 C1 C0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0

"1" "1" "1"

Address bits

Command bits( V )

Data bits

ACK0

DO

DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0

Data Communication protocol

( V ) Command bits (C2, C1, C0) = (1, 1, 1)

3

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