HI3086(1997) 查看數據表（PDF） - Intersil

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HI3086
(Rev.:1997)

6-Bit, 140 MSPS, Flash A/D Converter

Intersil 

HI3086

CLK

CLK

HI3086

CLK A

RESETN

6-BITS

CLKOUT

DATA

HI3086

CLK B

RESETN

6-BITS

CLKOUT

DATA

FIGURE 8. WHEN THE RESET PULSE IS NOT USED

CLK

HI3086

CLK A

RESETN

6-BITS

CLK

RESET

PULSE

CLKOUT

DATA

RESET PULSE

HI3086

CLK B

RESETN

6-BITS

CLKOUT

DATA

FIGURE 9. WHEN THE RESET PULSE IS USED

Straight Mode (See Figures 22, 23, 24 and 25).

Digital Input Level and Supply Voltage Settings

Set the SELECT pin to GND for this mode. In this mode,

data output can be obtained in accordance with the clock fre-

quency applied to the A/D converter for applications which

use the clock applied to the A/D converter as the system

clock.

The A/D converter can operate at fC (Min) = 100 MSPS in

this mode.

The logic input level for the HI3086 supports ECL, PECL and

TTL levels. The power supplies (DVEE3, DGND3) for the

logic input block must be set to match the logic input (CLK

and RESET signals) level.

TABLE 3. LOGIC INPUT LEVEL AND POWER SUPPLY SETTINGS

DIGITAL

INPUT

LEVEL

ECL

DVEE3

-5V

DGND3

0V

SUPPLY APPLICATION

VOLTAGE CIRCUITS

±5V

Figures 19, 22

PECL

0V

+5V

+5V

Figures 20, 23

TTL

0V

+5V

+5V Figures 21, 24, 25

4-1416

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