MCF52110 查看數據表（PDF） - Freescale Semiconductor
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MCF52110 Datasheet PDF : 54 Pages
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MCF52110 Family Configurations
1 MCF52110 Family Configurations
Table 1. MCF52110 Family Configurations
Module
52100
52110
ColdFire Version 2 Core with MAC (Multiply-Accumulate Unit)
•
•
System Clock
66, 80 MHz
Performance (Dhrystone 2.1 MIPS)
up to 76
Flash / Static RAM (SRAM)
64/16 Kbytes
128/16 Kbytes
Interrupt Controller (INTC)
•
•
Fast Analog-to-Digital Converter (ADC)
•
•
Real-Time Clock (RTC)
•
•
Four-channel Direct-Memory Access (DMA)
•
•
Software Watchdog Timer (WDT)
•
•
Backup Watchdog Timer
•
•
Two-channel Periodic Interrupt Timer (PIT)
2
2
Four-Channel General Purpose Timer (GPT)
•
•
32-bit DMA Timers
4
4
QSPI
•
•
UART(s)
I2C
2
3
2
2
Eight/Four-channel 8/16-bit PWM Timer
•
•
General Purpose I/O Module (GPIO)
•
•
Chip Configuration and Reset Controller Module
•
•
Background Debug Mode (BDM)
JTAG - IEEE 1149.1 Test Access Port1
•
•
•
•
Package
64 LQFP/QFN
81 MAPBGA
64 LQFP/QFN
81 MAPBGA
100 LQFP
1 The full debug/trace interface is available only on the 100-pin packages. A reduced debug interface is
bonded on smaller packages.
MCF52110 ColdFire Microcontroller, Rev. 0
Freescale Semiconductor
3
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