MCF5271 查看數據表（PDF） - Freescale Semiconductor
零件编号
产品描述 (功能)
生产厂家
MCF5271 Datasheet PDF : 56 Pages
| |||
Features
3.11 DMA Timers (DTIM0-DTIM3)
There are four independent, DMA-transfer-generating 32-bit timers (DTIM[3:0]) on the MCF5271. Each
timer module incorporates a 32-bit timer with a separate register set for configuration and control. The
timers can be configured to operate from the system clock or from an external clock source using one of
the DTINn signals. If the system clock is selected, it can be divided by 16 or 1. The input clock is further
divided by a user-programmable 8-bit prescaler which clocks the actual timer counter register (TCRn).
Each of these timers can be configured for input capture or reference compare mode. By configuring the
internal registers, each timer may be configured to assert an external signal, generate an interrupt on a
particular event or cause a DMA transfer.
3.12 Periodic Interrupt Timers (PIT0-PIT3)
The four periodic interrupt timers (PIT[3:0]) are 16-bit timers that provide precise interrupts at regular
intervals with minimal processor intervention. Each timer can either count down from the value written in
its PIT modulus register, or it can be a free-running down-counter.
3.13 Software Watchdog Timer
The watchdog timer is a 16-bit timer that facilitates recovery from runaway code. The watchdog counter
is a free-running down-counter that generates a reset on underflow. To prevent a reset, software must
periodically restart the countdown.
3.14 Clock Module and Phase Locked Loop (PLL)
The clock module contains a crystal oscillator (OSC), frequency modulated phase-locked loop (PLL),
reduced frequency divider (RFD), status/control registers, and control logic. To improve noise immunity,
the PLL and OSC have their own power supply inputs, VDDPLL and VSSPLL. All other circuits are
powered by the normal supply pins, VDD and VSS.
3.15 Interrupt Controllers (INTC0/INTC1)
There are two interrupt controllers on the MCF5271, each of which can support up to 63 interrupt sources
each for a total of 126. Each interrupt controller is organized as 7 levels with 9 interrupt sources per level.
Each interrupt source has a unique interrupt vector, and 56 of the 63 sources of a given controller provide
a programmable level [1-7] and priority within the level.
3.16 DMA Controller
The Direct Memory Access (DMA) Controller Module provides an efficient way to move blocks of data
with minimal processor interaction. The DMA module provides four channels (DMA0-DMA3) that allow
byte, word, longword or 16-byte burst line transfers. These transfers are triggered by software explicitly
setting a DCRn[START] bit. Other sources include the DMA timer, external sources via the DREQ signal,
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2
10
Freescale Semiconductor
Share Link: 