PCF5270VM100 查看數據表（PDF） - Freescale Semiconductor

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PCF5270VM100

MCF5271 Integrated Microprocessor Hardware Specification

Freescale Semiconductor 

Features

To support program trace, the Version 2 debug module provides processor status (PST[3:0]) and debug

data (DDATA[3:0]) ports. These buses and the PSTCLK output provide execution status, captured operand

data, and branch target addresses defining processor activity at the CPU’s clock rate.

3.4 JTAG

The MCF5271 supports circuit board test strategies based on the Test Technology Committee of IEEE and

the Joint Test Action Group (JTAG). The test logic includes a test access port (TAP) consisting of a 16-state

controller, an instruction register, and three test registers (a 1-bit bypass register, a 330-bit boundary-scan

register, and a 32-bit ID register). The boundary scan register links the device’s pins into one shift register.

Test logic, implemented using static logic design, is independent of the device system logic.

The MCF5271 implementation can do the following:

• Perform boundary-scan operations to test circuit board electrical continuity

• Sample MCF5271 system pins during operation and transparently shift out the result in the

boundary scan register

• Bypass the MCF5271 for a given circuit board test by effectively reducing the boundary-scan

register to a single bit

• Disable the output drive to pins during circuit-board testing

• Drive output pins to stable levels

3.5 On-chip Memories

3.5.1 Cache

The 8-Kbyte cache can be configured into one of three possible organizations: an 8-Kbyte instruction

cache, an 8-Kbyte data cache or a split 4-Kbyte instruction/4-Kbyte data cache. The configuration is

software-programmable by control bits within the privileged Cache Configuration Register (CACR). In all

configurations, the cache is a direct-mapped single-cycle memory, organized as 512 lines, each containing

16 bytes of data. The memories consist of a 512-entry tag array (containing addresses and control bits) and

a 8-Kbyte data array, organized as 2048 x 32 bits.

If the desired address is mapped into the cache memory, the output of the data array is driven onto the

ColdFire core's local data bus, completing the access in a single cycle. If the data is not mapped into the

tag memory, a cache miss occurs and the processor core initiates a 16-byte line-sized fetch. The cache

module includes a 16-byte line fill buffer used as temporary storage during miss processing. For all data

cache configurations, the memory operates in write-through mode and all operand writes generate an

external bus cycle.

3.5.2 SRAM

The SRAM module provides a general-purpose 64-Kbyte memory block that the ColdFire core can access

in a single cycle. The location of the memory block can be set to any 64-Kbyte boundary within the

4-Gbyte address space. The memory is ideal for storing critical code or data structures, for use as the

MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2

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Freescale Semiconductor

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