MCM63Z916TQ15 查看數據表（PDF） - Motorola => Freescale
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MCM63Z916TQ15 Datasheet PDF : 35 Pages
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Freescale Semiconductor, Inc.
MCM63Z916 PBGA PIN DESCRIPTIONS
Pin Locations
Symbol
4B
ADV
4K
CK
4M
(a) 6D, 7E, 6F, 7G, 6H, 7K, 6L, 6N, 7P
(b) 1D, 2E, 2G, 1H, 2K, 1L, 2M, 1N, 2P
5J, 5R
CKE
DQx
FT
4F
G
3R
LBO
2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C, 5C,
6C, 4G, 2R, 6R, 2T, 3T, 5T, 6T
4N, 4P
SA
SA1, SA0
5L, 3G
SBx
(a) (b)
4E
SE1
2B
SE2
6B
SE3
4H
SW
4U
TCK
3U
TDI
5U
TDO
2U
TMS
6U
TRST
4C, 2J, 3J, 4J, 6J, 1R, 4R
1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U
3D, 5D, 3E, 5E, 3F, 5F, 5G, 3H, 5H, 3K,
5K, 3L, 3M, 5M, 3N, 5N, 3P, 5P, 7T
4A, 1B, 7B, 1C, 7C, 2D, 4D, 7D, 1E, 6E,
2F, 1G, 6G, 2H, 7H, 1K, 6K, 2L, 4L, 7L,
6M, 2N, 7N, 1P, 6P, 7R, 1T, 4T
VDD
VDDQ
VSS
NC
Type
Description
Input Synchronous Load/Advance: Loads a new address into counter when
low. RAM uses internally generated burst addresses when high.
Input Clock: This signal registers the address, data in, and all control signals
except G and LBO.
Input Clock Enable: Disables the CK input when CKE is high.
I/O Synchronous Data I/O: “x” refers to the byte being read or written
(byte a, b).
Input
Flow–Through Option Input: This pin must remain in steady state (this
signal is not registered or latched). It must be tied high or low.
Low — flow–through functionality.
High — pipelined functionality.
Input Asynchronous Output Enable.
Input
Linear Burst Order Input: This pin must remain in steady state (this
signal not registered or latched). It must be tied high or low.
Low — linear burst counter.
High — interleaved burst counter.
Input Synchronous Address Inputs: These inputs are registered and must
meet setup and hold times.
Input
Synchronous Address Inputs: These pins must be wired to the two
LSBs of the address bus for proper burst operation. These inputs are
registered and must meet setup and hold times.
Input Synchronous Byte Write Inputs: Enables write to byte “x” (byte a, b) in
conjunction with SW. Has no effect on read cycles.
Input Synchronous Chip Enable: Active low to enable chip.
Input Synchronous Chip Enable: Active high for depth expansion.
Input Synchronous Chip Enable: Active low for depth expansion.
Input Synchronous Write: This signal writes only those bytes that have been
selected using the byte write SBx pins.
Input
Input
Boundary Scan Pin, Test Clock: If boundary scan is not used, TCK
must be tied to VDD or VSS.
Boundary Scan Pin, Test Data In.
Output Boundary Scan Pin, Test Data Out.
Input Boundary Scan Pin, Test Mode Select.
Input
Supply
Boundary Scan Pin, Asynchronous Test Reset. If boundary scan is not
used, TRST must be tied to VSS.
Core Power Supply.
Supply I/O Power Supply.
Supply Ground.
— No Connection: There is no connection to the chip.
MCM63Z834•MCM63Z916
8
For More Information On This Product,
Go to: www.freescale.com
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