MCP1623 查看數據表（PDF） - Microchip Technology
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MCP1623 Datasheet PDF : 30 Pages
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MCP1623/24
3.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE
MCP1623/24
SOT-23
2x3 DFN
Symbol
1
5
SW
2
—
GND
3
4
EN
4
1
FB
5
—
VOUT
6
8
VIN
—
2
SGND
—
3
PGND
—
7
VOUTS
—
6
VOUTP
—
9
EP
Description
Switch Node, Boost Inductor Input Pin
Ground Pin
Enable Control Input Pin
Feedback Voltage Pin
Output Voltage Pin
Input Voltage Pin
Signal Ground Pin
Power Ground Pin
Output Voltage Sense Pin
Output Voltage Power Pin
Exposed Thermal Pad (EP); must be connected to VSS.
3.1 Switch Node Pin (SW)
Connects the inductor from the input voltage to the SW
pin. The SW pin carries inductor current and can be as
high as 425 mA peak. The integrated N-Channel switch
drain and integrated P-Channel switch source are
internally connected at the SW node.
3.2 Ground Pin (GND)
The ground or return pin is used for circuit ground
connection. Length of trace from input cap return, output
cap return and GND pin should be made as short as
possible to minimize noise on the GND pin.
3.3 Enable Pin (EN)
The EN pin is a logic-level input used to enable or
disable device switching and lower quiescent current
while disabled. A logic high (greater than 90% of VIN)
will enable the regulator output. A logic low (less than
20% of VIN) will ensure that the regulator is disabled.
3.4 Feedback Voltage Pin (FB)
The FB pin is used to provide output voltage regulation
by using a resistor divider. The FB voltage will be 1.21V
typical with the output voltage in regulation.
3.5 Output Voltage Pin (VOUT)
The output voltage pin connects the integrated
P-Channel MOSFET to the output capacitor. The FB
voltage divider is also connected to the VOUT pin for
voltage regulation.
3.6 Power Supply Input Voltage Pin
(VIN)
Connects the input voltage source to VIN. The input
source should be decoupled to GND with a 4.7 µF
minimum capacitor.
3.7 Signal Ground Pin (SGND)
The signal ground pin is used as a return for the
integrated VREF and error amplifier. In the 2x3 DFN
package, the SGND and power ground (PGND) pins are
connected externally.
3.8 Power Ground Pin (PGND)
The power ground pin is used as a return for the
high--current N-Channel switch. In the 2x3 DFN
package, the PGND and signal ground (SGND) pins are
connected externally.
3.9 Output Voltage Sense Pin (VOUTS)
The output voltage sense pin connects the regulated
output voltage to the internal bias circuits. In the
2x3 DFN package, VOUTS and VOUTP are connected
externally.
3.10 Output Voltage Power Pin (VOUTP)
The output voltage power pin connects the output
voltage to the switch node. High current flows through
the integrated P-Channel and out of this pin to the
output capacitor and output. In the 2x3 DFN package,
VOUTS and VOUTP are connected externally.
3.11 Exposed Thermal Pad (EP)
There is an internal electrical connection between the
Exposed Thermal Pad (EP) and the VSS pin; they must
be connected to the same potential on the Printed
Circuit Board (PCB).
2010-2016 Microchip Technology Inc.
DS40001420D-page 9
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