MCP23009T-E/P 查看數據表（PDF） - Microchip Technology

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MCP23009T-E/P

8-Bit I/O Expander with Open-Drain Outputs

Microchip Technology 

MCP23009/MCP23S09

1.3.3 SPI INTERFACE

The MCP23S09 operates in Mode 0,0 and Mode 1,1.

The difference between the two modes is the idle state

of the clock.

• Mode 0,0: The idle state of the clock is low. Input

data is latched on the rising edge of the clock; out-

put data is driven on the falling edge of the clock.

• Mode 1,1: The idle state of the clock is high. Input

data is latched on the rising edge of the clock; out-

put data is driven on the falling edge of the clock.

1.3.3.1 SPI Write Operation

The SPI write operation is started by lowering CS. The

write command (slave address with R/W bit cleared) is

then clocked into the device. The opcode is followed by

an address and at least one data byte.

1.3.3.2 SPI Read Operation

The SPI read operation is started by lowering CS. The

SPI read command (slave address with R/W bit set) is

then clocked into the device. The opcode is followed by

an address, with at least one data byte being clocked

out of the device.

1.3.3.3 SPI Sequential Write/Read

For sequential operations, instead of deselecting the

device by raising CS, the master clocks the next byte

pointed to by the address pointer (see Section 1.3.1

“Byte Mode and Sequential Mode” for details

regarding sequential operation control).

The sequence ends by the raising of CS.

The MCP23S09 address pointer will roll over to

address zero after reaching the last register address.

 2009-2014 Microchip Technology Inc.

DS20002121C-page 7

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