MCP4017T-502E 查看數據表（PDF） - Microchip Technology
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MCP4017T-502E Datasheet PDF : 66 Pages
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MCP4017/18/19
TABLE 1-2: I2C BUS DATA REQUIREMENTS (SLAVE MODE)
I2C AC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C ≤ TA ≤ +125°C (Extended)
Operating Voltage VDD range is described in AC/DC characteristics
Parame- Sym Characteristic
ter No.
Min
Max Units
Conditions
100
THIGH Clock high time 100 kHz mode
4000
—
ns 1.8V-5.5V
400 kHz mode
600
—
ns 2.7V-5.5V
101
TLOW Clock low time 100 kHz mode
4700
—
ns 1.8V-5.5V
400 kHz mode
1300
—
ns 2.7V-5.5V
102A (5) TRSCL SCL rise time
100 kHz mode
400 kHz mode
—
1000
20 + 0.1Cb 300
ns Cb is specified to be from
ns 10 to 400 pF
102B (5) TRSDA SDA rise time
100 kHz mode
400 kHz mode
—
1000
20 + 0.1Cb 300
ns Cb is specified to be from
ns 10 to 400 pF
103A (5) TFSCL SCL fall time
100 kHz mode
—
300
400 kHz mode 20 + 0.1Cb 40
ns Cb is specified to be from
ns 10 to 400 pF
103B (5) TFSDA SDA fall time
100 kHz mode
—
300
400 kHz mode 20 + 0.1Cb (4) 300
ns Cb is specified to be from
ns 10 to 400 pF
106 THD:DAT Data input hold 100 kHz mode
0
time
400 kHz mode
0
—
ns 1.8V-5.5V, Note 6
—
ns 2.7V-5.5V, Note 6
107 TSU:DAT Data input
100 kHz mode
250
setup time
400 kHz mode
100
—
ns (2)
—
ns
109
TAA Output valid
100 kHz mode
from clock
400 kHz mode
—
3450 ns (1)
—
900 ns
110
TBUF Bus free time 100 kHz mode
4700
400 kHz mode
1300
—
ns Time the bus must be free
—
ns before a new transmission
can start
TSP Input filter spike 100 kHz mode
—
suppression
400 kHz mode
—
(SDA and SCL)
50 ns Philips Spec states N.A.
50 ns
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2: A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the
requirement tsu; DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not
stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it
must output the next data bit to the SDA line
TR max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before
the SCL line is released.
3: The MCP4018/MCP4019 device must provide a data hold time to bridge the undefined part between VIH
and VIL of the falling edge of the SCL signal. This specification is not a part of the I2C specification, but must
be tested in order to guarantee that the output data will meet the setup and hold specifications for the receiv-
ing device.
4: Use Cb in pF for the calculations.
5: Not Tested.
6: A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do not
unintentionally create a Start or Stop condition.
DS22147A-page 10
© 2009 Microchip Technology Inc.
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