MH16S72APHB-6 查看數據表（PDF） - MITSUBISHI ELECTRIC
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MH16S72APHB-6 Datasheet PDF : 55 Pages
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Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH16S72APHB -6,-7,-8
1,207,959,552-BIT (16,777,216 - WORD BY 72-BIT)Synchronous DRAM
Serial Presence Detect Table I
Byte
Function described
0 Defines # bytes written into serial memory at module mfgr
1
Total # bytes of SPD memory device
2
Fundamental memory type
3
# Row Addresses on this assembly
4
# Column Addresses on this assembly
5
# Module Banks on this assembly
6
Data Width of this assembly...
7
... Data Width continuation
8
Voltage interface standard of this assembly
9 SDRAM Cycletime at Max. Supported CAS Latency (CL).
-6
Cycle time for CL=3
-7,-8
10
SDRAM Access from Clock
-6
tAC for CL=3
-7,-8
11
DIMM Configuration type (Non-parity,Parity,ECC)
12
Refresh Rate/Type
13
SDRAM width,Primary DRAM
14
Error Checking SDRAM data width
15 Minimum Clock Delay,Back to Back Random Column Addresses
16
Burst Lengths Supported
17
# Banks on Each SDRAM device
18
CAS# Latency
SPD enrty data
128
256 Bytes
SDRAM
A0-A11
A0-A9
1BANK
x72
0
LVTTL
7.5ns
10ns
5.4ns
6ns
ECC
self refresh(15.625uS)
x8
x8
1
1/2/4/8/Full page
4bank
2/3
19
CS# Latency
20
Write Latency
21
SDRAM Module Attributes
22
SDRAM Device Attributes:General
0
0
non-buffered,non-registered
Precharge All,Auto precharge
23
SDRAM Cycle time(2nd highest CAS latency)
-6
Cycle time for CL=2
-7
-8
10ns
10ns
13ns
24
SDRAM Access form Clock(2nd highest CAS latency)
-6
6ns
tAC for CL=2
-7
6ns
-8
7ns
25
SDRAM Cycle time(3rd highest CAS latency)
26 SDRAM Access form Clock(3rd highest CAS latency)
27
Precharge to Active Minimum
-6
-7,-8
28
Row Active to Row Active Min.
-6
-7,-8
29
RAS to CAS Delay Min
-6
-7,-8
30
Active to Precharge Min
-6
N/A
N/A
22.5ns
20ns
15ns
20ns
22.5ns
20ns
45ns
-7,-8
50ns
SPD DATA(hex)
80
08
04
0C
0A
01
48
00
01
75
A0
54
60
02
80
08
08
01
8F
04
06
01
01
00
0E
A0
A0
D0
60
60
70
00
00
17
14
0F
14
17
14
2D
32
MIT-DS-0378-0.1
MITSUBISHI
ELECTRIC
( 4 / 55 )
17.Mar.2000
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