MIC3833 查看數據表（PDF） - Micrel

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MIC3833

Current-Fed PWM Controllers

Micrel 

MIC3832/3833

Micrel

Functional Description

PWM Comparator

Refer to the block diagram and Figure 5.

The MIC3832 and MIC3833 are self-contained controllers,

with a voltage reference, voltage-mode error amplifier; cur-

rent-mode, maximum duty cycle, overcurrent, and shutdown

comparators; and an undervoltage lockout circuit. Three

control loops are provided: voltage-mode through the error

amplifier, current-mode through the PWM comparator, and

overcurrent through the shutdown comparator. Three totem-

pole outputs provide up to 1A peak synchronized drive to

external FETs for current-fed push-pull or bridge transformer

applications.

Undervoltage Lockout (UVLO)

Undervoltage lockout (UVLO) requires that the input voltage

rise above 15.9V (MIC3832) or 8.3V (MIC3833) before the

startup circuit is energized. Once operating, the controller will

not shut down until the supply drops to 9.8V (MIC3832) or

7.8V (MIC3833). There is an internal 22V zener between VDD

and ground for overvoltage clamping. Zener current should

be limited to less than 20mA.

Voltage Reference (REF)

A sawtooth waveform is compared to the output of the error

amplifier. The sawtooth is generally the oscillator waveform

on CT in voltage-mode control systems. In current-mode

control systems, it is often the inductor current waveform.

Both systems result in a square wave output which, after

being NOR’ed with the MDC output (see below), is used to

drive the main (PWM) output stage.

PWM Latch and Output

The PWM latch is reset by an oscillator rising cycle, turning

the PWM output on if SHDN or UVLO are inactive. The PWM

comparator trips when the CMR rising ramp voltage exceeds

the error amplifier output voltage, setting the PWM latch and

terminating the PWM output, after a minimum time set by the

front edge blanking one-shot. If the output voltage is below

the setpoint, the PWM cycle is terminated at a maximum duty

cycle set by the voltage on the MDC/SS pin. If the output

voltage is above the setpoint, the error amplifier output is low,

and the PWM cycle terminates after the minimum set by the

front edge blanking one-shot. The PWM output is designed

to source and sink 1A peak into 1,000 pF loads. The output

is disabled when SHDN is enabled.

The reference consists of a 5V bandgap reference internally Push-Pull Outputs (Q and Q)

trimmed to 2% accuracy. It provides an internal reference

and can be used to supply up to 25mA to external circuits.

Two push-pull outputs are provided, with their leading edge

synchronized to alternating PWM rising ramp initiation. The

4

Oscillator (RT/CT)

two outputs are 180° out of phase, with a slight (50ns typ.)

The oscillator stage performs two functions. First, it provides overlap. The push-pull outputs are designed to source and

a linear sawtooth waveform which is fed to the PWM com- sink 1A peak into 1,000 pF loads. This peak current was

parator in voltage-mode control. Second, it toggles the flip- chosen to provide the designer with the option of using

flop which provides the Q and Q outputs. The oscillator bipolar, MOSFET, or IGBT switching elements. To minimize

frequency is configured using an external timing resistor and ringing on the output waveform, the series inductance seen

capacitor. A nominal voltage of 3.6V appears on the RT pin;

the resulting current is then mirrored through the CT pin which

charges the timing capacitor and generates the linear ramp.

by the drivers should be as low as possible. This can be

accomplished by keeping the distance between the MIC3832/

3 and the switching elements as short as possible, or by using

It is important to select an appropriate capacitor. At high

frequencies effective series resistance, effective series in-

ductance, dielectric loss and dielectric absorption all affect

frequency stability and accuracy. RF capacitors such as

silver mica, glass, polystyrene, or COG ceramics are recom-

carbon composition resistors in series with the FET gates.

The Q and Q outputs have a small overlap with no dead time.

While advantageous to current-fed topologies, other topolo-

gies may require slight modification to accommodate this

overlap. The outputs are disabled when SHDN is enabled.

mended. High K ceramics should not be used.

Maximum Duty Cycle (MDC)

Front-Edge Blanking

This feature provides a fixed delay time prior to current

sensing becoming active. This prevents the overcurrent

sensing function from being falsely tripped by initial system

transients. Timing is set to a nominal 140ns.

Error Amplifier (EA)

The error amplifier is an opamp with a low impedance output

that is used to sense output conditions and provide a dc

output based on those conditions to the PWM comparator.

The output of this stage is brought out to allow tailoring of the

closed loop gain or frequency response. The open loop gain

of this stage is typically 95dB. The inputs are diode clamped

to each other.

This feature, which uses the same pin as soft start (MDC/SS),

provides another method of limiting duty cycle. The voltage

seen by this pin determines the maximum duty cycle that can

be obtained from the PWM output. As this feature can vary

by as much as 15% over temperature, it is not recommended

that it be used in place of a well designed feedback loop.

The voltage on MDC/SS, the inverting input of the MDC

comparator, is compared to the voltage on CMR, with internal

front edge blanking.

For voltage-mode operation, refer to the graph, “Typical

Characteristics: Voltage-Mode Max. Duty Cycle vs. MDC

Voltage.” Voltage-mode operation requires the timing ca-

pacitor ramp, from CT, be connected directly to CMR.

April 1998

4-141

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