MIC5841 查看數據表（PDF） - Micrel

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MIC5841

8-Bit Serial-Input Latched Drivers

Micrel 

Micrel, Inc.

MIC5841/42

Timing Conditions

(TA = 25°C Logic Levels are VDD and VSS)

VDD = 5V

A. Minimum Data Active Time Before Clock Pulse (Data Set-Up Time)...................................................................... 75 ns

B. Minimum Data Active Time After Clock Pulse (Data Hold Time) ............................................................................ 75 ns

C. Minimum Data Pulse Width ................................................................................................................................... 150 ns

D. Minimum Clock Pulse Width................................................................................................................................... 150 ns

E. Minimum Time Between Clock Activation and Strobe ........................................................................................... 300 ns

F. Minimum Strobe Pulse Width.................................................................................................................................. 100 ns

G. Typical Time Between Strobe Activation and Output Transition............................................................................ 500 ns

SERIAL DATA present at the input is transferred to the shift register on the logic “0” to logic “1” transition of the CLOCK

input pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. The

SERIAL DATA must appear at the input prior to the rising edge of the CLOCK input waveform.

Information present at any register is transferred to its respective latch when the STROBE is high (serial-to-parallel

conversion). The latches will continue to accept new data as long as the STROBE is held high. Applications where the

latches are bypassed (STROBE tied high) will require that the ENABLE input be high during serial data entry.

When the ENABLE input is high, all of the output buffers are disabled (OFF) without affecting information stored in the

latches or shift register. With the ENABLE input low, the outputs are controlled by the state of the latches.

MIC5840 Family Truth Table

Serial

Data

Input

H

L

X

Clock

Input

Shift Register Contents

I1 I2 I3 … I8

H R1 R2 … R7

L R1 R2 … R7

R1 R2 R3 … R8

X X X…X

P1 P2 P3 … P8

L = Low Logic Level

H = High Logic Level

X = Irrelevant

P = Present State

R = Previous State

Serial

Data

Output

R7

R7

R8

X

P8

Strobe

Input

Latch Contents

I1 I2 I3 … I8

Output

Enable

Output Contents

I1 I2 I3 … I8

L

R1 R2 R3 … R8

H P1 P2 P3 … P8

L

P1 P2 P3 … P8

X X X…X

H

H H H …H

May 2006

5

M9999-050506

(408) 955-1690

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