MK41T56 查看數據表（PDF） - STMicroelectronics
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MK41T56 Datasheet PDF : 15 Pages
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Table 9. Power Down/Up Mode AC Characteristics
(TA = 0 to 70°C or –40 to 85°C)
Symbol
Parameter
tPD
SCL and SDA at VIH before Power Down
tFB
VPFD (min) to VSO VCC Fall Time
tRB
VSO to VPFD (min) VCC Rise Time
tREC
SCL and SDA at VIH after Power Up
Figure 5. Power Down/Up Mode AC Waveforms
MK41T56, MKI41T56
Min
Max
Unit
0
ns
300
µs
100
µs
200
µs
VCC
VPFD
VSO
tPD
SDA
SCL
IBAT
tFB
tRB
DATA RETENTION TIME
tREC
AI00595
OPERATION (cont’d)
The clock continually monitors VCC for an out of
tolerance condition. Should VCC fall below VPFD,
the device terminates an access in progress and
resets the device address counter. Inputs to the
device will not be recognized at this time to prevent
erroneous data from being written to the device
from an out of tolerance system. When VCC falls
below VBAT, the device automatically switches over
to the battery and powers down into an ultra low
current mode of operation to conserve battery life.
Upon power-up, the device switches from battery
to VCC at VBAT and recognizes inputs when VCC
goes above VPFD volts.
2-WIRE BUS CHARACTERISTICS
This bus is intended for communication between
different ICs. It consists of two lines: one bi-direc-
tional for data signals (SDA) and one for clock
signals (SCL). Both the SDA and the SCL lines
must be connected to a positive supply voltage via
a pull-up resistor.
The following protocol has been defined:
– Data transfer may be initiated only when the
bus is not busy.
– During data transfer, the data line must remain
stable whenever the clock line is High.
– Changes in the data line while the clock line is
High will be interpreted as control signals.
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