MK41T56 查看數據表（PDF） - STMicroelectronics

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MK41T56

512 bit (64b x8) Serial Access TIMEKEEPER® SRAM

STMicroelectronics 

Figure 6. Serial Bus Data Transfer Sequence

DATA LINE

STABLE

DATA VALID

CLOCK

MK41T56, MKI41T56

DATA

START

CONDITION

CHANGE OF

DATA ALLOWED

STOP

CONDITION

AI00587

Figure 7. Acknowledgement Sequence

SCLK FROM

MASTER

START

1

DATA OUTPUT

BY TRANSMITTER

DATA 1

DATA OUTPUT

BY RECEIVER

2

DATA 2

CLOCK PULSE FOR

ACKNOWLEDGEMENT

8

9

DATA 8

AI00588

Figure 8. Bus Timing Requirements Sequence

SDA

tBUF

SCL

P

tHD:STA

tR

tF

tHIGH

S

tLOW

tSU:DAT

tHD:DAT

tHD:STA

tSU:STA

SR

tSU:STO

P

AI00589

7/15

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