ML4804IS 查看數據表（PDF） - Fairchild Semiconductor
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ML4804IS Datasheet PDF : 14 Pages
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ML4804
PIN CONFIGURATION
ML4804
16-Pin PDIP (P16)
16-Pin Narrow SOIC (S16N)
IEAO 1
16 VEAO
IAC 2
ISENSE 3
VRMS 4
SS 5
15 VFB
14 VREF
13 VCC
12 PFC OUT
VDC 6
RAMP 1 7
11 PWM OUT
10 GND
RAMP 2 8
9 DC ILIMIT
TOP VIEW
PIN DESCRIPTION
PIN NAME
1 IEAO
2 IAC
3 ISENSE
4 VRMS
5 SS
6 VDC
7 RAMP 1
8 RAMP 2
FUNCTION
Slew rate enhanced PFC
transconductance error amplifier output
PFC AC line reference input to Gain
Modulator
Current sense input to the PFC Gain
Modulator
PFC Gain Modulator RMS line voltage
compensation input
Connection point for the PWM soft start
capacitor
PWM voltage feedback input
Oscillator timing node; timing set
by RTCT
When in current mode, this pin
functions as the current sense input;
when in voltage mode, it is the PWM
modulation ramp input.
PIN NAME
9
DC ILIMIT
FUNCTION
PWM cycle-by-cycle current
limit comparator input
10 GND
Ground
11 PWM OUT PWM driver output
12 PFC OUT PFC driver output
13 VCC
14 VREF
Positive supply
Buffered output for the internal
7.5V reference
15 VFB
PFC transconductance voltage
error amplifier input
16 VEAO
PFC transconductance voltage
error amplifier output
2
REV. 1.0.2 3/9/2001
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