MMDJ-65609EV-40MQ 查看數據表（PDF） - Atmel Corporation

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MMDJ-65609EV-40MQ

Rad. Hard 128K x 8 3.3-volt Very Low Power CMOS SRAM

Atmel Corporation 

Write Cycle 3. CS1 or CS2

Controlled(1)

Note:

1. The internal write time of the memory is defined by the overlap of CS1 LOW and CS2 HIGH and W LOW. Both signals must

be activated to initiate a write and either signal can terminate a write by going in activated. The data input setup and hold

timing should be referenced to the actived edge of the signal that terminates the write. Data out is high impedance if OE =

VIH.

10 M65609E

4158D–AERO–06/02

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