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PS11016

FLAT-BASE TYPE INSULATED TYPE

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MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>

PS11016

FLAT-BASE TYPE

INSULATED TYPE

Fig. 8 INVERTER OUTPUT ANALOGUE CURRENT SENSING AND SIGNALING TIMING CHART

off

VCIN

on

on

V(hold)

off

IC

0

+ICL

(VS)

0

Ref

VC

0

off

VCL on

N-side IGBT Current

t(hold)

Delay time

td(read)

N-side FWDi Current

–ICL

Fig. 9 START-UP SEQUENCE

Fig. 10 RECOMMENDED I/O INTERFACE CIRCUIT

Normally at start-up, Fo and CL output signals will be pulled-up

High to Supply voltage (OFF level); however, FO1 output may fall to

Low (ON) level at the instant of the first ON input pulse to an N-Side

5V

IGBT. This can happen particularly when the boot-strap capacitor is

of large size. FO1 resetting sequence (together with the boot-strap

charging sequence) is explained in the following graph

ASIPM

DC-Bus voltage

VPN 0

Control voltage supply

VDH 0

Boot-strap voltage

N-Side input signal

VDB

0

VCIN(N)

on

PWM starts

a)

CPU

b)

5.1kΩ

R

R

10kΩ

0.1nF 0.1nF

UP,VP,WP,UN,VN,WN,Br

F01,F02,F03,CL

CU,CV,CW

GND(Logic)

P-Side input signal VCIN(P) on

Brake input signal

FO1 output signal

VCIN(Br) on

FOI on

a) Boot-strap charging scheme :

Apply a train of short ON pulses at all N-IGBT input pins for ad-

equate charging (pulse width = approx. 20µs number of pulses =10

~ 500 depending on the boot-strap capacitor size)

b) FO1 resetting sequence:

Apply ON signals to the following input pins : Br → Un/Vn/Wn →

Up/Vp/Wp in that order.

Jan. 2000

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