AD7818ARM(2000) 查看數據表（PDF） - Analog Devices
零件编号
产品描述 (功能)
生产厂家
AD7818ARM
(Rev.:2000)
(Rev.:2000)
Analog Devices
AD7818ARM Datasheet PDF : 16 Pages
| |||
AD7816/AD7817/AD7818
TIMING CHARACTERISTICS1, 2 (VDD = +2.7 V to +5.5 V, GND = 0␣ V, REFIN = +2.5␣ V. All specifications TMIN to TMAX unless
otherwise noted)
Parameter A, B Versions Units
Test Conditions/Comments
tPOWER-UP
2
t1a
9
t1b
27
t2
20
t3
50
t4
0
t5
0
t6
10
t7
10
t8
40
t9
40
t10
0
t11
0
t123
20
t133
20
t14a3, 4
30
t14b3, 4
30
t15
150
t16
40
t17
400
µs max
µs max
µs max
ns min
ns max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns max
ns max
ns max
ns min
ns min
Power-Up Time from Rising Edge of CONVST
Conversion Time Channels 1 to 4
Conversion Time Temperature Sensor
CONVST Pulsewidth
CONVST Falling Edge to BUSY Rising Edge
CS Falling Edge to RD/WR Falling Edge Setup Time
RD/WR Falling Edge to SCLK Falling Edge Setup
DIN Setup Time before SCLK Rising Edge
DIN Hold Time after SCLK Rising Edge
SCLK Low Pulsewidth
SCLK High Pulsewidth
CS Falling Edge to RD/WR Rising Edge Setup Time
RD/WR Rising Edge to SCLK Falling Edge Setup Time
DOUT Access Time after RD/WR Rising Edge
DOUT Access Time after SCLK Falling Edge
DOUT Bus Relinquish Time after Falling Edge of RD/WR
DOUT Bus Relinquish Time after Rising Edge of CS
BUSY Falling Edge to OTI Falling Edge
RD/WR Rising Edge to OTI Rising Edge
SCLK Rising Edge to CONVST Falling Edge (Acquisition Time of T/H)
NOTES
1Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 1␣ ns (10% to
90% of +5 V) and timed from a voltage level of +1.6␣ V.
2See Figures 16, 17, 20 and 21.
3These figures are measured with the load circuit of Figure 3. They are defined as the time required for D OUT to cross 0.8 V or 2.4 V for VDD = 5 V ± 10% and 0.4 V
or 2 V for VDD = 3 V ± 10%, as quoted on the specifications page of this data sheet.
4These times are derived from the measured time taken by the data outputs to change 0.5␣ V when loaded with the circuit of Figure 3. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
Specifications subject to change without notice.
200A
IOL
TO
OUTPUT
PIN
CL
50pF
200A
IOL
1.6V
Figure 3. Load Circuit for Access Time and Bus Relinquish Time
REV. A
–5–
Share Link: