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MM74HC175N 查看數據表(PDF) - Fairchild Semiconductor

零件编号
产品描述 (功能)
生产厂家
MM74HC175N
Fairchild
Fairchild Semiconductor Fairchild
MM74HC175N Datasheet PDF : 7 Pages
1 2 3 4 5 6 7
AC Electrical Characteristics
VCC = 5V, TA = 25°C, CL = 15 pF, tr = tf = 6 ns
Symbol
Parameter
fMAX
tPHL, tPLH
tPHL, tPLH
tREC
tS
tH
tW
Maximum Operating
Frequency
Maximum Propagation
Delay, Clock to Q or Q
Maximum Propagation
Delay, Reset to Q or Q
Minimum Removal
Time, Clear to Clock
Minimum Setup Time, Data to Clock
Minimum Hold Time, Data from Clock
Minimum Pulse Width, Clock or Clear
Conditions
Guaranteed
Typ
Units
Limit
60
35
MHz
15
25
ns
13
21
ns
20
ns
20
ns
0
ns
10
16
ns
AC Electrical Characteristics
VCC = 2.0V to 6.0V, CL = 50 pF, tr = tf = 6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
VCC
TA = 25°C
Typ
TA = −40 to 85°C TA = −55 to 125°C Units
Guaranteed Limits
fMAX
Maximum Operating
Frequency
2.0V
12
6
5
4.5V
60
30
24
4
MHz
20
MHz
6.0V
70
35
28
24
MHz
tPHL, tPLH Maximum Propagation
Delay, Clock to Q or Q
2.0V
80
150
190
4.5V
15
30
38
225
ns
45
ns
6.0V
13
26
32
38
ns
tPHL, tPLH Maximum Propagation
Delay, Reset to Q or Q
2.0V
64
125
158
4.5V
14
25
32
186
ns
37
ns
6.0V
12
21
27
32
ns
tREM
Minimum Removal Time
Clear to Clock
2.0V
4.5V
100
125
20
25
150
ns
30
ns
6.0V
17
21
25
ns
tS
Minimum Setup Time
Data to Clock
2.0V
4.5V
100
125
20
25
150
ns
30
ns
6.0V
17
21
25
ns
tH
Minimum Hold Time
Data from Clock
2.0V
4.5V
0
0
0
0
0
ns
0
ns
6.0V
0
0
0
ns
tW
Minimum Pulse Width
Clear or Clock
2.0V
30
80
100
4.5V
9
16
20
120
ns
24
ns
6.0V
8
14
17
20
ns
tr, tf
Maximum Input Rise and
Fall Time
2.0V
4.5V
1000
500
1000
500
1000
ns
500
ns
6.0V
400
400
400
ns
tTLH, tTHL Maximum
Output Rise and
2.0V
30
75
95
4.5V
9
15
19
110
ns
22
ns
Fall Time
6.0V
8
13
16
19
ns
CPD
Power Dissipation
(per package)
150
pF
Capacitance (Note 5)
CIN
Maximum Input
Capacitance
5
10
10
10
pF
Note 5: CPD determines the no load dynamic power consumption, PD=CPD VCC2f+ICC VCC, and the no load dynamic current consumption,
IS=CPD VCC f+ICC.
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