MH8S72BBFD-7 查看數據表（PDF） - MITSUBISHI ELECTRIC

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MH8S72BBFD-7

603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

MITSUBISHI ELECTRIC  

P rSepl iemci.n a r y

MITSUBISHI LSIs

MH8S72BBFD-7, -8

603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

COMMAND TRUTH TABLE

COMMAND

Deselect

No Operation

MNEMONIC

CK

n-1

CK

n

DESEL

NOP

HX

HX

/S /RAS /CAS /WE BA

HX X X X

LH H H X

A10 A0-9

XX

XX

Row Adress Entry &

Bank Activate

ACT

H XL L H H V V V

Single Bank Precharge

Precharge All Bank

Column Address Entry

& Write

PRE

PREA

WRITE

H XL L H L

H XL L H L

H X L LH H L

VL X

VHX

VL V

Column Address Entry

& Write with Auto-

WRITEA H X L H L L V H V

Precharge

Column Address Entry

& Read

READ

H XL H L H V L V

Column Address Entry

& Read with Auto

Precharge

Auto-Refresh

Self-Refresh Entry

Self-Refresh Exit

Burst Terminate

Mode Register Set

READA

REFA

REFS

REFSX

TERM

MRS

H XL H L H V H V

H H L HL L H X X X

H LLL L H X X X

L H H LX X X X X X

L HL H H H X X X

H XL H H L X X X

H X L L L L L L V*1

H =High Level, L = Low Level, V = Valid, X = Don't Care, n = CK cycle number

NOTE:

1.A7-9 = 0, A0-6 = Mode Address

MIT-DS-0228-0.2

MITSUBISHI

ELECTRIC

29/Oct. /1998

6

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