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MP1567

1.2A Synchronous Rectified Step-Down Converter

Monolithic Power Systems 

TM

MP1567 – 1.2A SYNCHRONOUS RECTIFIED STEP-DOWN CONVERTER

output voltage ripple is mostly independent of

the ESR. The output voltage ripple is estimated

to be:

VRIPPLE

=

1.4

×

VIN

×

⎜⎜⎝⎛

fLC

fSW

⎟⎟⎠⎞ 2

Where VRIPPLE is the output ripple voltage, VIN is

the input voltage, fLC is the resonant frequency

of the LC filter and fSW is the switching

frequency. In the case of tantalum or low-ESR

electrolytic capacitors, the ESR dominates the

impedance at the switching frequency, and so

the output ripple is calculated as:

VRIPPLE = ∆I × RESR

Where ∆I is the inductor ripple current, and

RESR is the equivalent series resistance of the

output capacitors.

Choose an output capacitor to satisfy the output

ripple requirements of the design. A 10µF

ceramic capacitor is suitable for most

applications.

Selecting the Inductor

The inductor is required to supply constant

current to the output load while being driven by

the switched input voltage. A larger value

inductor results in less ripple current that will

results in lower output ripple voltage. However,

the larger value inductor has a larger physical

size, higher series resistance and/or lower

saturation current. Choose an inductor that

does not saturate under the worst-case load

conditions. A good rule for determining the

inductance is to allow the peak-to-peak ripple

current to be approximately 30% of the

maximum load current. Make sure that the peak

inductor current (the load current plus half the

peak-to-peak inductor ripple current) is below

2A to prevent loss of regulation due to the

current limit.

Calculate the required inductance value by the

equation:

L = VOUT × (VIN − VOUT )

VIN × fSW × ∆I

Compensation

The system stability is controlled through the

COMP pin. COMP is the output of the internal

transconductance error amplifier. A series

capacitor-resistor combination sets a pole-zero

combination to control the characteristics of the

control system.

The DC loop gain is:

A VDC

=

A VEA

× GCS

× RLOAD

×

⎜⎜⎝⎛

VFB

VOUT

⎟⎟⎠⎞

Where AVEA is the transconductance error

amplifier voltage gain, GCS is the current sense

gain (roughly the output current divided by the

voltage at COMP) and RLOAD is the load

resistance (VOUT/IOUT where IOUT is the output

load current)

The system has 2 poles of importance, one is

due to the compensation capacitor (C3), and

the other is due to the load resistance and the

output capacitor (C2). The first is:

fP1

=

2π ×

GEA

A VEA

×

C3

Where P1 is the first pole and GEA is the error

amplifier transconductance (300µA/V). The

second is:

fP2

=

1

2π × RLOAD

× C2

The system has one zero of importance, due to

the compensation capacitor (C3) and the

compensation resistor (R3). The zero is:

f Z1=

1

2π × R3 × C3

If large value capacitors with relatively high

equivalent-series-resistance (ESR) are used,

the zero due to the capacitance and ESR of the

output capacitor can be compensated by a third

pole set by R3 and C4. This pole is:

fP3

=

1

2π × R3 × C4

The system crossover frequency (the frequency

where the loop gain drops to 1, or 0dB) is

important. Set the crossover frequency to

MP1567 Rev. 2.3

www.MonolithicPower.com

7

1/3/2006

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